Analysis of photodepopulation of electron traps in HfO2 films grown by atomic layer deposition is shown to provide the trap energy distribution across the entire oxide bandgap. The presence is revealed of two kinds of deep electron traps energetically distributed at around Et ≈ 2.0 eV and Et ≈ 3.0 eV below the oxide conduction band. Comparison of the trapped electron energy distributions in HfO2 layers prepared using different precursors or subjected to thermal treatment suggests that these centers are intrinsic in origin. However, the common assumption that these would implicate O vacancies cannot explain the charging behavior of HfO2, suggesting that alternative defect models should be considered.

The work describes the physical principles of the exhaustive photodepopulation spectroscopy. This method allows one to determine the energy distribution of gap states in insulating materials using the observation of optically-assisted electron removal from the gap states in incremental spectral windows. Examples of the inferred energy distributions of acceptor-type electron states in several high-k oxide insulators (Al2O3, HfO2, GdxAl2-xO3) indicate that these are »1-2 eV broad. At the same time, no detectable density of donor states, expected to be present due to oxygen vacancies, is found in the studied oxides.

The effective work function (EWF) and the energy position of the valence band in 20‐40‐nm thick VO2and V2O5layers grown by atomic layer deposition (ALD) on top of insulating SiO2 and γ‐Al2O3 films were evaluated using the comparison between capacitance‐voltage and internal photoemission measurements. From the capacitance measured at different temperatures on the metal‐VO2(V2O5)‐insulator‐silicon and metal‐insulator‐silicon diodes we found that the both studied vanadium oxides have the same EWF as gold electrodes evaporated on the same oxides. This result is further collaborated by the internal photoemission experiments at the VO2/SiO2 and V2O5/SiO2 interfaces which indicate the energy barrier between the top of the vanadium oxide valence band (in the insulating phase) and the insulator conduction band to be 4.1 ± 0.1 eV. Since the transition from the narrow‐gap VO2 to the wide‐gap V2O5 oxide causes no change in the WF or in the photoemission threshold, we conclude that the ALD‐grown VO2 in its insulating phase represents a a heavily‐doped semiconductor which becomes metallic upon metal‐insulator transition without significant EWF change. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

In this work we analyse the influence of the O‐scavenging process on interface traps in (100)Si/SiOx/HfO2(1.8 nm)/TiNx/Si stacks by using electrical measurements and electron spin resonance spectroscopy. The reduction of interfacial SiOx by high‐temperature annealing in O‐free ambient is found to lead to severe interface degradation exposed as generation of additional Si dangling bond defects (paramagnetic Pb0 centres). The density of these centres, well known to be electron traps impairing device operation, increases from ∼1 × 1012 cm−2 – the value typical for thermally oxidized Si – to >3 × 1012 cm−2 upon annealing at 1100 °C. This interface degradation is accompanied by the development of a hysteresis in the MOS capacitance–voltage curves indicating generation of additional oxide traps with areal density in the range of 1012 cm−2. However, the trap generation can be alleviated if the O‐scavenging annealing step is performed in helium ambient, suggesting formation of silicon monoxide molecules at the Si/SiOx interface as the origin of the observed trap generation.

Scaling the planar NAND flash cells to the 20 nm node and beyond mandates introduction of inter‐gate insulators with high dielectric constant (κ). However, because these insulators provide a smaller electron barrier at the interface with the poly‐Si floating gate, the program window and the retention properties of these scaled cells are jeopardized. To reduce the charge loss from the floating to the control gate, one may consider the introduction of a hybrid floating gate (HFG) structure comprised of poly‐Si and a high work function (WF) metal, e.g., TiNx (x ∼ 1; WF ∼ 4.7 eV) or Ru (WF ∼ 5.3 eV). However, the very HFG concept is based on the assumption that electron trapping occurs inside the HFG stack rather than on traps present in the high‐κ insulator. To examine this critical hypothesis, we analyzed the energy distribution of electrons trapped in flash cells with poly‐Si(2 nm)/TiN (6 nm)/Hf0.8Al0.2Ox(19 nm, κ ∼ 15–19)/TiNx (10 nm) and Si(2 nm)/Ru (1 nm)/Hf0.8Al0.2Ox(5 nm)/Al2O3 (5 nm)/Hf0.8Al0.2Ox (5 nm)/TiNx (10 nm) trapping gate stacks using the exhaustive photo‐depopulation spectroscopy. We found that trapped electron energy levels show a broad distribution (± 0.3 eV) centred at ∼3.2 eV below the oxide conduction band. The energy onset of electron de‐trapping at ∼2.8 eV matches the TiNx/HfO2 barrier height found from internal photoemission experiments, indicating that electrons are predominantly trapped inside the HFG.