Selective-area growth is a promising technique for enabling of the fabrication of the scalable III–V nanowire networks required to test proposals for Majorana-based quantum computing devices. However, the contours of the growth parameter window resulting in selective growth remain undefined. Herein, we present a set of experimental techniques that unambiguously establish the parameter space window resulting in selective III–V nanowire networks growth by molecular beam epitaxy. Selectivity maps are constructed for both GaAs and InAs compounds based on in situ characterization of growth kinetics on GaAs(001) substrates, where the difference in group III adatom desorption rates between the III–V surface and the amorphous mask area is identified as the primary mechanism governing selectivity. The broad applicability of this method is demonstrated by the successful realization of high-quality InAs and GaAs nanowire networks on GaAs, InP, and InAs substrates of both (001) and (111)B orientations as well as homoepitaxial InSb nanowire networks. Finally, phase coherence in Aharonov–Bohm ring experiments validates the potential of these crystals for nanoelectronics and quantum transport applications. This work should enable faster and better nanoscale crystal engineering over a range of compound semiconductors for improved device performance.

The number of electrons in small metallic or semiconducting islands is quantised. When tunnelling is enabled via opaque barriers this number can change by an integer. In superconductors the addition is in units of two electron charges (2e), reflecting that the Cooper pair condensate must have an even parity. This ground state (GS) is foundational for all superconducting qubit devices. Here, we study a hybrid superconducting–semiconducting island and find three typical GS evolutions in a parallel magnetic field: a robust 2e-periodic even-parity GS, a transition to a 2e-periodic odd-parity GS, and a transition from a 2e- to a 1e-periodic GS. The 2e-periodic odd-parity GS persistent in gate-voltage occurs when a spin-resolved subgap state crosses zero energy. For our 1e-periodic GSs we explicitly show the origin being a single zero-energy state gapped from the continuum, i.e., compatible with an Andreev bound states stabilized at zero energy or the presence of Majorana zero modes.

The realization of hybrid superconductor–semiconductor quantum devices, in particular a topological qubit, calls for advanced techniques to readily and reproducibly engineer induced superconductivity in semiconductor nanowires. Here, we introduce an on-chip fabrication paradigm based on shadow walls that offers substantial advances in device quality and reproducibility. It allows for the implementation of hybrid quantum devices and ultimately topological qubits while eliminating fabrication steps such as lithography and etching. This is critical to preserve the integrity and homogeneity of the fragile hybrid interfaces. The approach simplifies the reproducible fabrication of devices with a hard induced superconducting gap and ballistic normal-/superconductor junctions. Large gate-tunable supercurrents and high-order multiple Andreev reflections manifest the exceptional coherence of the resulting nanowire Josephson junctions. Our approach enables the realization of 3-terminal devices, where zero-bias conductance peaks emerge in a magnetic field concurrently at both boundaries of the one-dimensional hybrids.