This work proposes an adaptive frequency-domain equalizer (FDE) for single carrier and OFDM indoor over Gbps data rate wireless receiver. System simulation and specifications are based on the IEEE 802.15.3c standard. The proposed LS-LMS FDE uses low computational complexity Least-MeanSquare (LMS) algorithm with Least-Square (LS) channel estimation to accelerate the convergence speed. The FDE can be used for dual mode (SC and HSI) Wireless Personal Area Networks (WPAN) system. The simulation results show that the LS-LMS FDE can achieve 1.32*10 -4 BER in SC mode and 6.55*10 -3 in HSI mode (both uncoded) at SNR 14 dB. The total area is about 415K gate-count with 69% shared among single carrier and OFDM mode except 2 FFT. The power consumption is only 81.27 mW when working at 400MHz. Keywords -Adaptive frequency-domain equalizer, Channel estimation, LMS, LS, Dual mode.I. 0BINT RODUCTION IEEE 802.15.3c standard focuses on the indoor over Gbps data rate wireless communication and operates at 60 GHz radio frequency band. The standard indicates that the system supports both single carrier and OFDM transmission. From the view of equalization, OFDM has advantage of inter-symbol-interference (ISI)-free property. To eliminate ISI, a cyclic prefix (CP) of length no less than the channel impulse response (CIR) is inserted in each of the transmitted OFDM symbol. Although OFDM is able to eliminate the ISI, it has the drawback of high peak-to-average power ratio (PAPR). Furthermore, OFDM suffers from inter-carrier-interference (ICI) caused by carrier frequency offset (CFO) or Doppler Effect, which ruins the orthogonality among each subchannels. On the other hand, single carrier system is less affected by PAPR and ICI than OFDM while using time-domain equalization. However, the ISI impacts the performance and the computational complexity of time-domain equalizer (TDE) is very high as the RMS delay spread of channel increasing. Research shows that when the CIR increases to certain length, the frequency-domain equalizer (FDE) has less computational complexity than the TDE [1]. With the aid of CP, the FDE can be implemented easily than ever before [2] [3]. Also, single carrier block transmission (SCBT) is formed when the CP partitions the continuous data stream into data blocks, like the symbols in OFDM. The number of subchannels is determined by the number of samples in one data block, which is 512 in IEEE 802.15.3c standard. Each of the subchannels occupies 3.375MHz (1728MHz/512 subchannels) bandwidth. Therefore, the SCBT with the FDE is free from ISI and only slightly affected by PAPR and ICI [4]. Furthermore, the proposed FDE can also be used for IEEE 802.15.3c HSI (OFDM) mode with modification to reduce the overhead of FFT.However, there are two major concerns in SCBT with FDE. First, unlike OFDM, there is no pilot subcarrier in SCBT so that the channel estimation method in OFDM can not be used in the FDE.Under the influence of Doppler Effect, doing equalization without updating the equalizer coefficients is unpractical. Without...
a first-reported 4Kx2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multistandard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm 2 . It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications. I.P 0 P 1 P 2 P 3 WORD Address 0 4 P 2 P 3 WORD Address BIT Address B 0 B 7 …… DA = 1 WA = 1, BA = 2
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm 2 . This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-ratedistortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For smartphone applications, it completes real-time HEVC encoding and decoding with 4096×2160 resolution and 30fps, and consumes 126.73mW (0.5nJ/pixel) of core power dissipation at 0.9V, at 494MHz (encoding) and 350MHz (decoding). 1080HD and 720HD resolutions are reported as well. The chip features are summarized in Fig. 18.6.1.
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