Advances in CMOS (Complementary Metal Oxide Semiconductor) device technology have helped reduce typical die core sizes by shrinking the minimum transistor feature size. In the case of wirebonded devices with high IO counts, the final die size is increasingly determined by the size and layout of the IO cells and corresponding wirebond pads. Typical wirebond pad designs consist of a top-level metal that does not include any circuitry beneath the bonding region. Further, placement rules typically require the placement of ESD circuitry, buffers, and busses inside of the bond pad ring in order to avoid possible damage and reliability failures caused by wirebonding. On die with high pad counts, this exclusion area can represent a significant percentage of the die area that is not used for circuitry.This papers describes a layout technology called Bond Over Active (BOA), that was developed to utilize this "excluded" region beneath wirebond pads in order to minimze die area. Two different BOA layouts are evaluated using a standard test structure. Wirebond assembly reliability and package stress reliability are determined. The transfer of forces from the top metal pad to the active silicon during wirebonding are predicted using mechanical simulations. The results of the simulations are used to explain the similar levels of reliability observed for the two BOA layouts.