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A fully electronic medium density DNA micro array is presented using a CMOS process extended by gold electrodes. The chip provides 128 sensor sites, in-sensor site current-mode A/D conversion, peripheral circuitry including bandgap and current references, D/A-converters to provide electrode bias voltages, calibration circuitry, and a 6 pin interface for power supply and serial digital data transfer.

Silicon front-end and assembly and packaging technology more and more merge. In addition interconnect density reaches limits for advanced CMOS technology. In this paper we introduce the fan-out embedded wafer level packaging technology, which is an example to link front-end and packaging technology and offers additional freedom for interconnect design. We demonstrate capabilites for system integration of the eWLB technology, which includes system on chip (SoC) integration and system in package (SiP) integration like side by side and stacking of devices. We highlight the importance of understanding properties of new materials, which influence warpage or heat dissipation. We also show the excellent performance of the eWLB package for mm-wave applications.

In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window