Power dissipation i n technology mapped circuits can be mduced by performing gate re-sizing. Recently w e have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate'the arrival times at each node of a circuit f o r any primary input .vector. I n this paper w e extend our timing analysis tool to the symbolic calculation of required times and slacks, and w e use this information to identify gates of the circuit that can be re-sized. The nice feature of our approach is that i t takes into account the presence of false paths naturally. As shown by the experimental results, circuits re-synthesized with the technique we present i n this paper are guaranteed t o be at least as fast as the original implementations, but smaller and substantially less power-consuming.

This paper presents a novel technique for re-synthesizing circuits for low-power dissipation. Power consumption is reduced through redundancy addition and removal by using learning to identify indirect logic implications within a circuit. Such implications are exploited by adding gates and connections to the circuit without altering its overall behavior and thereby enabling us to eliminate other, high power dissipating, n o des. We propose a new BDD-based method for computing indirect implications in a logic network; furthermore, we present heuristic techniques to perform redundancy addition and removal without destroying the topology of the mapped circuit. Experimental results show the eectiveness of the proposed t e chnique in reducing power while keeping within delay and area c onstraints.