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Using strained SiGe on Si, the threshold voltage of high PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2 O 3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high and metal gates for 32nm node and beyond. Introduction While excellent advances have been made in acheving low NMOS threshold voltage with high performance [1-3], a manufacturable low PMOS V T still remains a challenge. We demonstrate here the modulation of PMOS V T with substrate band gap rather than relying on metal work function alone. The device is then integrated into the PMOS region with La 2 O 3 capping in the NMOS region to attain symmetric CMOS devices on the same chip, both with high performance. DiscussionThe issues with achieving proper valence band-edge work function for high /metal gate stacks have been well chronicled. [4,5] In examining the threshold voltage equation,The term V FB is composed of the several charge terms and the metal-semiconductor work function difference, MS = Metal -semi . In reducing V Tp , researchers have searched for a metal with high Metal to maximize MS and offset the other terms in V Tp .[6] However, an alternate approach is to minimize semi . This can be done by incorporating Ge into the channel which is known to move the valence band toward the vacuum level. [7] A comparison of the 1µm I D -V G curves for >10% SiGe channel and control Si in Fig. 1 indicates there is a shift of ~300mV and that the drive current for the SiGe device is significantly higher than the Si. This phenomenon is seen for several metals that are within ¼E g of the valence band edge (Fig. 2). The lower threshold voltage is attributed to two mechanisms: the change in band gap due to Ge in the SiGe [7] with a minor contribution from compressive strain of epitaxial SiGe directly on Si. [8] This is shown pictorially in Fig. 3 where a metal with work function of ~4.9 eV [9] is lined up with the valence band of the epitaxial SiGe. In Fig. 4, the gate leakage and C-V of ALD HfSiO directly on SiGe display excellent properties with EOT= 1.25nm and J G = 9.2A/cm 2 .Since a SiGe channel can provide the right PMOS threshold voltage, it is of interest to combine it with known NMOS solutions and demonstrate high performance. The integration scheme for combining these elements on the same wafer is outlined in Fig. 5. [10] Afer the NMOS gate stack is deposited and masked off, the PMOS Si is slightly recessed and selective epitaxy of >10% SiGe is grown. The PMOS gate stack is then deposited and masked. After removal of the PMOS gate from the top of the NMOS mask, the hard masks are then removed and the poly is deposited. After this point standard planar CMOS processing is followed with 1070 o C activation anneal.Cross section TEMs of the PMOS devices at ~80nm and the gate stack HRTEM are seen in Fig. 6. The detai...

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