No abstract

A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much more smaller.

The key components in digital design are Half adders.They perform not only addition operations, but also many other functions such as subtraction, multiplication and division. Very Large-Scale Integrated circuits (VLSI) frequently requires adders of various bit widths from processors to Application Specific Integrated Circuits (ASICs). Recently reported logic style comparisons based on full-adder circuits claims that the Complementary Pass transistor Logic (CPL) is much more power-efficient than complementarymetal oxide semiconductor(CMOS). However, new comparisons are performed on more efficient (CMOS) circuit realizations and a wider range of different logic cells as well as the use of realistic circuit arrangements demonstrates that the (CMOS) is superior to (CPL) in most cases with respect to speed, area, power dissipation, and power-delay products. Even Adder designed using (CMOS) complementary metal oxide semiconductor technology can have more power as well as speed than that using (CMOS) technology. The most important and widely accepted matrices for measuring the quality of adder designs power dissipation,propagation delay, and area. The overall performance can be significantly improved by using arithmetic circuits. This paper describes the comparative performance of half adder designed using TANNER (EDA) Electronic Design Automation, using different (CMOS) logic design styles.