Montana State University's Space Science and Engineering Laboratory (SSEL) under support fi-om the Montana NASA Space Grant Consortium is engaged in an earth orbiting satellite student project that will carry a reproduction, using current-day technology, of the scientific payload flown on Explorer-1 in 1958 into a 650 km sunsynchronous polar orbit. On-board operations will be commanded by a Motorola MC68HC812A4 (HC12) microcontroller, chosen for its ease of use, processing power, and intrinsic features. Accompanying this will be an Integrated Device Technology CMOS Supersync First-in, First-Out (FIFO) IDT72291 150 Kbyte RAM chip, used for storing scientific data and system telemetry before downlink to ground station. The RAM was selected for the simplicity of the FIFO data flow. The HC12 is responsible for controlling antenna deployment, communication handling, and other system parameters. Using in-house Assembly code, the system has been designed to run an abbreviated main loop, using hardware and s o h a r e interrupts to call subroutines, thereby allowing the mission critical tasks to be on the main loop for nearly constant monitoring. System interrupts allow the HC12 to seamlessly collect payload data, attitude data, battery conditions (voltage, current, charge state, and temperature), bus voltage, bus current, processor temperature, and stability of the payload high voltage power supply. This interrupt method allows new payload routines to be added with little code modification, maximizing satellite modularity for future experiments aboard Montana State University Cubesats. The design has the advantage of utilizing a powerful microcontroller therein eliminating the need for many of the external components needed by other systems (analog-to-digital converters, serial communications interfaces, slave microcontrollers, etc.), while remaining simple to program and implement. This paper describes MEROPE'S computer subsystems in detail.
