Soldering technologies continue to evolve to meet the demands of the continuous miniaturisation of electronic products, particularly in the area of solder paste formulations used in the reflow soldering of surface mount devices. Stencil printing continues to be a leading process used for the deposition of solder paste onto printed circuit boards (PCBs) in the volume production of electronic assemblies, despite problems in achieving a consistent print quality at an ultra‐fine pitch. In order to eliminate these defects a good understanding of the processes involved in printing is important. Computational simulations may complement experimental print trials and paste characterisation studies, and provide an extra dimension to the understanding of the process. The characteristics and flow properties of solder pastes depend primarily on their chemical and physical composition and good material property data is essential for meaningful results to be obtained by computational simulation.This paper describes paste characterisation and computational simulation studies that have been undertaken through the collaboration of the School of Aeronautical, Mechanical and Manufacturing Engineering at Salford University and the Centre for Numerical Modelling and Process Analysis at the University of Greenwich. The rheological profile of two different paste formulations (lead and lead‐free) for sub 100 micron flip‐chip devices are tested and applied to computational simulations of their flow behaviour during the printing process.

PurposeThe study investigates the sub process behaviour in stencil printing of type‐6 and type‐7 particle size distribution (PSD) Pb‐free solder pastes to assess their printing limits.Design/methodology/approachTwo solder pastes were used in a design of experiments approach to find optimal printing parametersFindingsSolder paste printing has been achieved to ultimately produce 30 μm deposits at 60 μm pitch for full area array patterns using a type‐7 Pb‐free solder paste. For a type‐6 PSD solder paste, full area array printing was limited to 50 μm deposits at 110 μm pitch. However, for peripheral printing patterns, 50 μm deposits at 90 μm pitch were obtained. The disparities in the behaviour of the two paste types at different geometries can be attributed to differences in the sub‐processes of the stencil printing. The paste release of the type‐6 paste from the stencil apertures at fine pitch was superior to the type‐7 paste, which may be attributed to the finer particle paste producing an increased drag force along the stencil aperture walls. However, the type‐7 paste was able to fill the smallest aperture openings, ultimately to 30 μm, thus producing full array printing patterns at uniquely small pitches.Practical implicationsThis advancement in the stencil printing process has been made possible by refinements to both solder paste design and stencil manufacturing technology. Adjustments in the solder paste rheology have enabled successful printing at ultra fine pitch geometries. This, together with selecting appropriate printing parameters such as printing speed, pressure, print gap and separation speed, allows a practical printing process window. Moreover, advancements in stencil fabrication methods have produced “state‐of‐the‐art” stencils exhibiting very precisely defined aperture shapes, with smooth walls at very fine pitch, thus allowing for improved solder paste release at very small dimensions.Originality/valueThe results can be used to present a low cost solution for Pb‐free flip chip wafer bumping. Furthermore, the results indicate that type‐6 and type‐7 solder pastes should be applied to/selected for specific application geometries.

In this paper solder paste printing is reported at sub 100µm pitch using Pb-free solder paste with IPC type-6 (15-5µm) particle size distributions. The results confirm that consistent sized paste deposits can be produced onto wafers at ultra fine pitch geometries using a stencil printing process.

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The high-intensity, high-resolution x-ray source at the European Synchrotron Radiation Facility (ESRF) has been used in x-ray diffraction (XRD) experiments to detect intermetallic compounds (IMCs) in lead-free solder bumps. The IMCs found in 95.5Sn3.8Ag0.7Cu solder bumps on Cu pads with electroplated-nickel immersion-gold (ENIG) surface finish are consistent with results based on traditional destructive methods. Moreover, after positive identification of the IMCs from the diffraction data, spatial distribution plots over the entire bump were obtained. These spatial distributions for selected intermetallic phases display the layer thickness and confirm the locations of the IMCs. For isothermally aged solder samples, results have shown that much thicker layers of IMCs have grown from the pad interface into the bulk of the solder. Additionally, the XRD technique has also been used in a temperature-resolved mode to observe the formation of IMCs, in situ, during the solidification of the solder joint. The results demonstrate that the XRD technique is very attractive as it allows for nondestructive investigations to be performed on expensive state-of-the-art electronic components, thereby allowing new, lead-free materials to be fully characterized.