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In system-level synthesis, the graph describing the task may consist of a great number of vertices, thus the design algorithms (e.g. hardware-software partitioning, pipeline synthesis, etc.) may become extremely complicated. This difficulty is relaxed by decomposing the task description graph that is usually unavoidable in system-level synthesis. The decomposing algorithms unite certain vertices of the graph, thus the resulting graph consists of less vertices. However, loops may appear in the decomposed graph, even if the original graph was loop-free, that endangers the efficiency of the design algorithms. We propose an algorithm that generates allowable cuts. We prove that any decomposition made along these cuts always yields a loopfree graph. The method is demonstrated on a simple example. Incorporating optimization criteria in the cut generation is also discussed.

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This paper will introduce a computer aided reliability analysis system, IRAS, which is a Unix‐based software package. It provides the following features: a model builder, failure mode effect and criticality analysis (FMECA), fault tree synthesis and analysis (FTA) and real time fault location (RTFL). 1. The model builder allows the creation of reliability models for production systems, which are able to reflect the initiation and propagation of serious deviations outside the production and performance tolerances. The modelling procedure allows hierarchical modelling. 2. The failure mode effect and criticality analysis (FMECA) option uses the causal trees and cause‐consequence diagrams that are created automatically from the IRAS model data base. The trees can be analysed by the user and the basic events can be grouped according to their criticality, probability and severity. 3. The fault tree analysis and synthesis (FTA) option enables the graphical analysis of fault trees. The generated tree can be trimmed automatically or by the user. It is also possible to extract the minimal cut‐set from the complete tree. 4. RTFL enables the fast detection of the most probable fault locations in the system, during the continuous measuring of sensors of the production system and comparing the signals with the expected values of the stored operational vector. It alarms the user in case of serious deviations, thus reducing the out of work stage of the system by making quicker and more efficient reaction of the maintenance facility operators. The failure searching time reduction results in lower maintenance cost.

Relative motion of camera and environment results in such visual cues, which may characterize 3D motion as well as the 3D structure of the a-priori unknown environment. 3D navigation includes both tasks: motion and 3D structure estimation. Earlier we showed that navigation can be based on the KLT algorithm where feature-type visual cues (e.g. corners) are selected and tracked throughout the video frame sequence. Reliability and real-time feature of 3D reconstruction mainly depends on the specificities of selected algorithms and design metrics of implementation technology. The paper first summarizes the theoretical background of the KLT feature tracking algorithm. Then hardware-software partition alternatives are evaluated in more detail resulting in FPGA implementations optimizing speed and cost. The pipeline structure of the hardware proved to be necessary due of the great amount of data which should be processed continuously as fast as possible. This work has been motivated by various real-time applications described in other papers.[8], [9].