Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors ͑MOSFETs͒. Substrate options are overviewed. A dislocation reduction anneal Ͼ800°C decreases threading dislocation densities for Ge-on-Si wafers 10-fold to 10 7 cm −2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ϳ6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for pϩ/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H 2 anneal for device performance is shown.

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Germanium possesses higher bulk mobilities than silicon and was used for the first transistors. However, by the 1960s its use was largely supplanted with Si due largely to Si's high quality thermal oxide. Today, with the 45 nm technology node in production, high k dielectrics are beginning to replace SiO2 in the gate, and as such, one of the key reasons for using Si is no longer as relevant. This, combined with performance concerns for Si based devices for and beyond the 22 nm node has made Ge a worthy area for research for high performance devices. In this paper, we give an overview of some of the major issues for Ge MOSFETs, illustrating recent progress using data from IMEC. Key results include a factor of 10 reduction in threading dislocations for epi Ge on Si by the use of an ~850{degree sign}C anneal, the first successful use of As halo implants, progress on optimization of activation anneals, the use of a thin epitaxial Si passivation and its impact on threshold voltage, a 2-step anneal NiGe process flow to drastically reduce defects, and the importance of a hydrogen anneal following metallization.