Abstract:The real time anticipation of robotic task is important in finding and correcting the error in CPU of robot, which may designed using by bit parallel-iterative CORDIC circuit. This paper proposed pass transistor logic based multiplexer, register, full adder and basic logic gates that are implemented into bit parallel-iterative CORDIC basic circuits. The circuits are designed using by DSCH2 CAD tool and layout are generated by microwind 3 CAD tool. The parameter analysis done by BSIM4 analyzer. The CPL CORDIC circuit is compared with conventional and CMOS CORDIC circuits that give better performance in terms of speed, power consumption and area. The analyses are extended to Fast Fourier Transformation (FFT). Keywords: robot, bit parallel-iterative, CORDIC algorithm, FFT, PTL Classification: Electron devices, circuits, and systems References[1] C. C. Sun and J. Götze, "A VLSI design concept for parallel iterative algorithms," Adv.