TXFor an LTE transceiver it is quite challenging to reduce power and area while preserving performance. For large emitted signals the TX dominates power consumption but in the past this situation was sufficiently infrequent not to affect energy consumption. In recent times the statistical distribution of the TX power has shifted upward due to the use of data-intensive communications and the introduction of multi-gain power amplifiers. Therefore to extend battery life in fourth generation terminals, TX consumption at high power (>-10dBm) should be reduced. A second challenge of an FDD LTE TX is noise and distortion emission in the RX band since the TX-to-RX distance, relative to the channel bandwidth, can be much smaller than in previous standards [1].A typical RF TX includes DAC, baseband filter, upconverter and pre-power amplifier (PPA). In some cases the PPA is not used and incorporated in the power mixer. This solution draws more current but reduces noise as shown in equation 1 that expresses the mixer signal-to-noise ratio (SNR) as a function of its gm stage bias current (Ibias), for Class-A operation and a given transistor overdrive voltage Vov.(1) From equation (1), the SNR ratio varies as follows. First it increases with bias current. Second it deteriorates with signal Peak-to-Average Ratio (PAR). Third it improves with transistor overdrive. A Class-A power mixer requires a minimum bias current to deliver its target power, which decreases as the output swing is increased. If this current is higher than that required to achieve the target noise in the RX band (for a given duplexer), the use of a PPA becomes feasible. However other considerations may discourage such a choice. First the PPA degrades Counter Intermodulation (CIM) and the Adjacent-Channel Leakage Ratio (ACLR). Second lowering noise emission allows the use of a lower selectivity duplexer which may result in cost savings and/or reduced losses [2].To reduce the bias current of a Class-A power mixer through an increase of its output swing, while limiting overall power consumption the authors in [3] have biased the mixer from 2.7V and the rest of the TX from 1.5V. This requires two high-efficiency switch-mode supplies and stresses the technology. A better solution is to use a Class-A/B power mixer that saves power and reduces noise [4]. The latter because the gm stage current noise is proportional to its average transconductance, which is equal to half of its peak value in Class A and much less in Class A/B especially for high PAR signals.Class A/B operation is achieved by placing in front of the mixer a differential voltage-to-current converter (V-to-I) whose output transistors are biased with a current much smaller than the peak signal current. A conceptual schematic of the V-to-I converter is shown in Fig. 19.7.1. The circuit performs three main functions. First it converts (via Rin) the voltage signal at the filter output into two differential currents that are sourced and sunk by the two push-pull output stages. For good linearity both differen...

AbstractmThis It is shown that an IC implementation of a Viterbi decoder based on a nonmiuimui trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered. Index TermsmACS-arrayarchitecture, trellis diagram, Viterbi decoder.

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A key element in the signal path of magnetic-disk read channels employing digital implementations of PRML and other discrete-time signalling approaches is the analog-to-digital (A/ D) interface containing a pre-filter, sampler, and analog-todigital converter (ADC). The pre-filter performs noise filtering, anti-aliasing, and pre-equalization prior to sampling and conversion to the digital domain. At symbol rates of lOOMHz and above, envisioned in the future, implementation of the required filtering is difficult using conventional approaches. This paper describes a filter/ADC combination that uses a switched-capacitor (SC) FIR passive sampling approach to implement the pre-filter [l -31. Parallelism in the signal path allows higher maximum filter bandwidth for a given technology than otherwise possible using conventional filtering techniques. The use of parallelism removes the speed limitation of amplifier settling time on filter bandwidth typical of conventional SC filters and is used throughout the signal path to reduce the speed requirements on all circuitry including the A/ D converter.The basic concept of the filtering approach is shown in Figure la. Closely-spaced clock edges sequentially turn off the sampling switches for an array of capacitors weighted as the impulse response of the desired filter. After one complete impulse response interval, charge on the capacitor array is equal to the sum of the products of the input voltage a t each sampling instant and its respective sampling capacitor. Multiple capacitor arrays operating in a staggered manner as shown in Figure l b provide an output a t the desired rate. By taking more than one sample per output period, a decimation filter is realized. The maximum sampling rate is limited by the spacing of clock phases. The use of a tapped ring oscillator allows the phases to be spaced one gate delay apart, allowing, if necessary, sampling rates into the GHz range. The sampling bandwidth is a function of switch size and technology. Since charge injection can be made signal-independent by using a bottom-plate differential arrangement, sampling bandwidth can be made very high. After sampling is complete, accumulated charge on an array is dumped to an SC integrator (amplifier with feedback capacitor) to convert the charge to a voltage.Important performance limitations of the parallel filter architecture come from sampling jitter, capacitor ratio error, mismatches in the offset voltages of the parallel stages, sampling skews between parallel stages, and the effects of finite amplifier gain [4]. Offset cancellation techniques are possible but difficult to implement as the degree of parallelism is increased. As a result, the performance of filters based on this technique is best suited to applications requiring modest accuracy but high speed. Speed is limited by the trade-off between complexity of increased numbers of parallel stages and effects of channel mismatches.This filtering approach is used in a prototype pre-filter/ADC implementationin both a decimationlowpass fi...