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lnmos Corp. Colorado Springs, COAN 8K X 8 EEPROM with internal high voltage generation for 5-volt-only operation, will be discussed. Double-poly, N-channel silicon gate Nitrox technology has been used to achieve a very small cell area. External interface hardware is eliminated for most applications by an internal programlerase controller. Latched program/erase commands free the system from waiting. Parallel row programming results in a 64 times decrease in programming time, compared to other EEPROMs, and provides single or multiple byte modify Capability.al biases are shown in Figure 16. The central poly-2 gate, with its nitride-oxide (Nitrox) dielectric, forms the nonvolatile storage region. The poly-1 isolation gate allows the source diffusion to be common to all memory cells in the array. This avoids an extra ground line for every column of memory cells; as required in a previous EEPROM'. The result is a cell area of 1 6 7~~ with 3p design rules. The entire memory array is in a P-well which is isolated from a second P-well in which all peripheral circuitry is built.Parallel row programming is implemented; 64 bytes can be programmed in one 1Oms operation. As shown in Figure 2, the array consists of 128 rows of 64 bytes each. There is a single row (64 bytes) of column latches. These latches store the data used to program a row. These data can be written directly from the data-in pins in random access fashion under control of column addresses A 0 -AS. This is done in the LOAD-BYTE cycle. During a PROGRAM operation, the data in these column latches are programmed in parallel into all 64 bytes of the row selected by addresses A6 -A12. This results in a 64 times programming time decrease compared t o single-byte programming.