A discharge-path-based sensing circuit is proposed to reduce the damage caused by an ovonic threshold switch (OTS) snapback current to a phase-change memory (PCM). OTS devices are used as access devices (selectors) in most PCM systems to increase the sensitivity and resolve the leakage current problem that occurs during sensing of the PCM cell. Snapback current, which occurs during an OTS phase change by using the OTS device, causes damage to the PCM device and deteriorates the read performance; thus, this study proposes a discharge path circuit as a new sensing method to reduce the damage inflicted on the PCM. In addition, a gate-coupled PMOS (GCPMOS) and a current mirror using a feed-forward technique are designed to reduce the peak value of the energy applied to the PCM. The discharge path circuit, GCPMOS, and the current mirror are designed in a 180-nm CMOS process and occupy an area of 0.19-mm 2 . The measurement results after fabrication show that, compared to the conventional sense amplifier based scheme, the discharge path circuit reduces the amount of energy applied to the PCM by 21.8%, and the discharge path circuit with the GCPMOS reduces the total energy consumption by 27.7%. Furthermore, the discharge path circuit with a feed-forward current mirror reduces the initial peak level of the PCM current by 10.1% and the total energy consumption by 34.6%. The proposed sensing circuit is the first snapback protection circuit reported to the public domain.

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This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies.