The transition and implementation of digital substations according to IEC61850 standard has changes in the testing methodology and the commissioning of these substations. The development of the Process Bus (IEC51850-9-2) in digital substations has allowed the transmission of secondary signals of voltage and current as sampled digital signals synchronized in time, this exchange of information can cause a loss of synchronism between IEDs in the process bus and the consequences during their operation must be known before they start operating. The real-time sampling of published currents and voltages with a time stamp in the process bus can also generate congestion that implies a loss / delay of SV that affects the performance of the IED.The methodology proposed in this work allows to study the individual response of an IED connected to the process bus for different SV contingencies. To study its response, an algorithm developed in MODELS is used, which performs a synchronized sampling of the currents and voltages calculated by the ATP and by means of "Hardware in The Loop -HIL-" technique, it emulates the behavior of a virtual Merging Unit publishing SV directly to the IED according to the IEC61850-9-2 protocol. Simulations carried out in ATP allow to evaluate the response of a phase overcurrent function, every study case consider a systemic loss of SV; the operation, signaling and trip omissions of the IED are recorded in each specific sequence of loss / delay of SV on the process bus.