In this study, we propose a layout technique to reduce the chip area of differential RF CMOS power amplifiers in which input and output transformers are utilized as input and output baluns. To minimize the chip area of the CMOS power amplifier, we split a conventional spiral transformer into two identical parts, thereby making full use of the wasted area in the conventional power amplifier. Using the proposed split transformers in the input and output transformers, we successfully reduce the chip area of the CMOS power amplifier based on a differential structure. To verify the feasibility of the proposed split cascode structure, we designed a 2.4‐GHz CMOS power amplifier using a 180‐nm SOI RF CMOS process. With an IEEE 802.11n WLAN modulated signal, we obtain a maximum output power of 9.73 dBm. From the measured results, we verify the feasibility of the proposed split transformer structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1443–1446, 2016

In this work, we propose a power amplifier using a stacked NMOS, transformer, and a PMOS structure to enhance the reliability of CMOS power amplifiers. The power stage of the amplifier is separated into NMOS and PMOS amplifier stages to moderate the peak voltages at the drains of each NMOS and PMOS. The power generated in the 2 amplifier stages is combined in the transformer, which has 2 primary parts and 1 secondary part. To verify the functionality of the structure, we designed a 2.4‐GHz differential CMOS power amplifier for IEEE 802.11n WLAN applications with 64 quadrature amplitude modulation, 9.6 dB peak‐to‐average power ratio, and a bandwidth of 20 MHz. The designed power amplifier is fabricated using the 180‐nm silicon‐on‐insulator RF CMOS process. The measured maximum linear output power is 17.88 dBm with a gain of 24.34 dB.