Billion transistor systems-on-chip increasingly require dynamic management of their hardware components and careful coordination of the tasks that they carry out. Diverse real-time monitoring functions assist towards this objective through the collection of important system metrics, such as throughput of processing elements, communication latency, or resource utilization for each application. The online evaluation of these metrics can result in localized or global decisions that attempt to improve aspects of system behavior, system performance, quality-of-service, power and thermal effects under nominal conditions. This work provides a comprehensive categorization of monitoring approaches used in multiprocessor SoCs. As adaptive systems are encountered in many disciplines, it is imperative to present the prominent research efforts in developing online monitoring methods. To this end we offer a taxonomy that groups strongly related techniques that designers increasingly use to produce more efficient and adaptive chips. The provided classification helps to understand and compare architectural mechanisms that can be used in systems, while one can envisage the innovations required to build real adaptive and intelligent systems-on-chip.

In recent years, due to the continuous development in the field of silicon technology, it is possible to implement complex electronic systems in a single integrated circuit. Systemson-Chip (SoC) have favored the explosion of the market of electronic appliances: small mobile devices, which provide communications and information capabilities for consumer electronics and industrial automation. These devices require complex electronic and high levels of system integration and need to be delivered in a very short time in order to meet their market window.The design complexity of these systems requires new design methodologies and the development of a seamless design flow that integrates existing and emerging tools. The International Technology Roadmap for Semiconductors (ITRS) [1] and MEDEA+ roadmap [2] evidence some key points that Electronic Design Automation Companies must consider in order to deal with such design complexity, among them: 1 2 CHAPTER 1. POWER OPTIMIZATION AND RELIABILITY ISSUES • Intellectual Property Reuse Intellectual Property (IP) reuse is becoming critical for an efficient system development; the need to shorten the time to market is stimulating re-usability of both hardware and software. A good way to keep design costs under control is to minimize the amount of new designs that are required each time a new SoC is developed: reuse existing design components where possible. The development of reusable IPs requires:the development of standards, including general constraints and guidelines, as well as executable specifications for intra-and inter-company IP exchange, such as Sys-temC, XML and UML [3],the creation of parameterizable, qualified and validated IPs, the use of hierarchical reuse methodology, allowing the reuse of the IPs and of the testbenches at different levels of abstraction.Furthermore, the IP reuse methodology is indispensable when the design of a system is developed in cooperation between different companies, or when the design center is distributed all over the world and consequently the project management is distributed. A lot of work have been done in the development of standards for IP qualification. The SPIRIT Consortium [4] developed the IP-XACT specification to enable rapid, reliable deployment of IPs into advanced design environments. The Virtual Socket Interface Alliance (VSIA) [5] developed the international standard QIP (Quality Intellectual Property) for measuring IP quality. OpenCores [6] is the world's largest community for development of open source hardware IPs. • Low Power DesignThe continuous progress of micro and nano technologies led to a growing integration and clock frequency increment in electronics systems. These combined effects lead to an increment both in power density and energy dissipation, with important consequences above all in portable systems. Some design and technology issues related to power efficiency are becoming crucial, in particular for power optimized cell-libraries, clockgating and clock-trees optimization, and dynamic power management. ...

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the onchip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segmentlevel based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environ- ment, coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption.We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

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