Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs) generation which is more resistant to physical attacks. We evaluate the physical phenomenon that the initial state of a 6T-SRAM cell is highly dependent on the process variations, which enables us to use the standard SRAM circuit, as a Physical Unclonable Function (PUF). Important requirements to serve as a PUF are that the start-up values of an SRAM circuit are uniquely determined, unpredictable and similar each time the circuit is turned on. We present the evaluation results of the internal SRAM memories of low power ICs as PUFs and the statistical analysis of the results. The experimental results prove that the low power 90nm commercial 6T-SRAMs are very useful as a PUF. As far as we know, this is the first work that provides an extensive evaluation of 6T-SRAM-based PUF, at different environmental, electrical, and ageing conditions to representing the typical operating conditions of a WSN.

Physical unclonable functions (PUFs) are relatively new security primitives used for device authentication and device-specific secret key generation. In this paper we focus on SRAM-PUFs. The SRAM-PUFs enjoy uniqueness and randomness properties stemming from the intrinsic randomness of SRAM memory cells, which is a result of manufacturing variations. This randomness can be translated into the cryptographic keys thus avoiding the need to store and manage the device cryptographic keys. Therefore these properties, combined with the fact that SRAM memory can be often found in today's IoT devices, make SRAM-PUFs a promising candidate for securing and authentication of the resource-constrained IoT devices. PUF observations are always effected by noise and environmental changes. Therefore secret-generation schemes with helper data are used to guarantee reliable regeneration of the PUF-based secret keys. Error correction codes (ECCs) are an essential part of these schemes. In this work, we propose a practical error correction construction for PUF-based secret generation that are based on polar codes. The resulting scheme can generate 128-bit keys using 1024 SRAM-PUF bits and 896 helper data bits and achieve a failure probability of 10 −9 or lower for a practical SRAM-PUFs setting with bit error probability of 15%. The method is based on successive cancellation combined with list decoding and hash-based checking that makes use of the hash that is already available at the decoder. In addition, an adaptive list decoder for polar codes is investigated. This decoder increases the list size only if needed. AuthenticationResponse N Y PUF Encoder Enrollment Key Server Helper data PUF Device Authentication N X Database Decoder N Y Helper data PUF DeviceĤ ash( ) S Hash Hash( ) S Hash Key SŜ Hash( ) S Verification

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver [1-3] is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mW for RX and 4.4mW for TX. Figure 13.2.1 shows the architecture of the RF SoC. An all-digital TX consists of a sub-mW snapshot-TDC all-digital PLL (ADPLL) [4] and an energy-efficient Class-D PA. A sliding-IF RX is adopted because it does not require a powerhungry LO generation. The PA with partial on-chip impedance matching and the LNA are both single-ended, which reduce external components and simplify the antenna interface design. A multistandard DBB [5] includes all PHY processing and data link for BLE and IEEE802.15.4. In this work the DBB further includes optimized HW/SW register interfaces and HW accelerators for protocol support, and implements an AHB/APB interface to facilitate integration with an ARM Cortex TM -M0 MCU and 128kB SRAM.One of the most challenging parts of the BLE RX mode is to receive the packets with an extremely short 8b preamble, which requires fast automatic gain control (AGC) and carrier-frequency offset (CFO) compensation method. A two-step AGC algorithm performs only coarse gain tuning in the RF parts (i.e., LNA and mixers) during the preamble with 12dB/step, allowing the RX output amplitude to quickly settle within the ADC dynamic range in just a few symbol periods. The fine amplitude tuning is performed in the LPF/PGA during the access code period with 3dB/step. Furthermore, BLE also specifies that the RX should accommodate a "dirty TX" with a large CFO up to ±100kHz (±41ppm). The CFO could be post-compensated in the DBB with a phase rotator, but then the LPF BW needs to be at least 100kHz wider, which compromises the adjacent channel rejection. In this work, a mixed-mode CFO compensation through an ADPLL allows direct compensation in the analog domain without increasing LPF BW. The CFO is first estimated by the DBB based solely on a part of the packet's preamble. The CFO estimation unit employs a 17-tap FIR filter with low latency. The CFO is detected by converting the IQ data to phase difference, and averaging it across preamble symbols. The CFO is then compensated by directly adjusting the fractional-N ADPLL with a frequency resolution of 1kHz. However, PLLs typically have a slow settling in the order of 20μs, which is not fast enough to compensate the CFO within the preamble. Therefore, the 2-point injection technique emp...

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