Nowadays, FPGA has become a very useful platform for multiple digital applications. Initially, the hardware programming languages like VHDL or Verilog were the only method for designing the FPGA. In this method, the designer should be able to transform the algorithm of the application into digital blocks. This consumes time and effort. Recently MATLAB realized the FPGA importance and decided to introduce a new tool for FPGA Design; this tool is MATLAB HDL Coder. The idea is to write a very easy MATLAB script and it will be converted to HDL using HDL Coder. Then this HDL code will go through the FPGA regular implementation path. This paper studies and compares, by example, the two methods. The comparison is done for Speed, FPGA utilization, and time for design/implementation. The digital unit under test was AES. The choice of this unit is based on having large input data, it makes many feedbacks, and It needs high speed. The test result doesn't recommend MATLAB HDL Coder for implementation but it recommends it to fast-proof ideas and fast prototypes. This is because the idea of just writing a simple script describing the algorithm results in a very complicated combinational circuit, which has a very low frequency. The recommended future research is to find a way to force the MATLAB script to be implemented in pipeline architecture. The expected result is to improve the performance in two directions utilization and frequency, but It'll lose the main advantage which is fast implementation.

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Background Information security is very important in today’s digital world, especially cybersecurity. The most common requirement in securing data in all services: confidentiality, digital signature, authentication, and data integrity is generating random keys. These random keys should be tested for randomness. Hardware security is more recommended than software. Hardware security has more speed and less exposure to many attacks than software security. Software security is vulnerable to attacks like buffer overflow attacks, side-channel attacks, and Meltdown–Spectre attacks. Results In this paper, we propose an FPGA Implementation for the adaptive digital chaotic generator. This algorithm is proposed and tested before. We introduce its implementation as hardware. This algorithm needs a random number seed as input. We propose two designs. The first one has an input random number. The second one has PRNG inside. The target FPGA is Xilinx Spartan 6 xc6slx9-2-cpg196. We used MATLAB HDL Coder for the design. We propose a configurable Key block’s length. For 32 bit the maximum frequency is 15.711 MHz versus 11.635 MHz for the first and second designs respectively. The area utilization of the Number of Slice Registers is 1% versus 2%. The number of Slice Look Up Tables is 40% versus 59%. number of bonded input output blocks is 64% versus 66%. otherwise are the same for the two designs. Conclusions In this paper, we propose an efficient and configurable FPGA Design for adaptive digital chaotic key generator. Our design has another advantage of storing the output keys internally and reading them later.

Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency. Results In this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique. Conclusions We used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design.