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Polycrystalline silicon TFTs with different front-and back-gate lengths are investigated. In addition, the laser annealing process yields high quality directional grains that enable us to orient TFT channels parallel or perpendicular to the grain boundaries. It is demonstrated that double-gate TFTs are fully depleted and therefore back interface properties exert critical influence to the overall TFT electrical performance. More specifically, it is demonstrated that the back interface contains a large number of defects, resulting in a deterioration of carrier conductance.

The DC stress induced device degradation of sequential lateral solidification (SLS) polysilicon thin film transistors (TFTs) was investigated by monitoring the threshold voltage in the linear regime of operation. Devices with different channel widths were compared. It was observed that the degradation of device parameters during hot carrier experiments was dependent on the channel width. The origin of this dependence is ascribed to self-heating effects.