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With the advent of self-configurable WSI, many candidates have been proposed for implementation and several have been produced.Trilogy set i~s sights on a supercomputer based on 40 ECL kilowatt wafers.Mosaic has reportedly delivered wafers with CMOS chips flip bonded on the wafer.Wafer Scale Integration, Inc. has announced its intent to produce CMOS wafers using a standard cell building block approach, and Sinclair has a~nounced a research effort based on the concepts of Ivor Catt x involving a wafer of serial shift register chips which self-connect to adjacent operable chips to form a wafer serial memory.NTT of Japan mounted a full wafer memory effort 2 using six memory modules of redundantly paired CMOS RAM chips.Most of the WSI projects have been based on memory elements since by their nature one element is like another and thus provide inherent redundancy, unlike unique logic elements (another possibility is specialized architecture~such as systolic processing using identical computing elements).A strong argument for memory wafers can be made by observing that the semiconductor industry is capable of producing a 32 bit wide multi-MIPS computer on a single chip while the demand for main memory remains insatiable. Thus an obvious candidate for wafer implementation is main memory. A recent paper 3 described the concept of wafer virtual memory (WAVM) which consists of a wafer of byte-wide off-the-shelf RAM's interconnected by a common bus on the wafer and used by treating bad RAM's as unavailable pages of a virtual memory. The only modification required to a conventional RAM is the addition of an address comparator so that each RAM can be uniquely addressed.In this architecture, the common bus is the focal point of both yield and performance:It must be small enough in total area to maintain a reasonable wafer yield while wide enough to allow an adequate transfer rate. Several techniques are available to enhance both yield and transfer rate.Yield of WSI is a mixture of two components--element yield and wafer yield.Element yield can be controlled at an acceptable level by utilizing smaller elements; e.g.~ a mature RAM of small area in lieu of a state-of-the-art RAM that pushes the size limits of reasonable yields.Another possibility is to create an element out of one half of a conventional RAM.Wafer yield is a function of the common bus and configuration logic.Since for WAVM the configuration logic is located with the using device, only the area of the common bus need be considered. To control bus yield if needed, the bus can be adjusted in size: 4

A taxonomy of configuration techniques for WSI is discussed and a metric for WSI efficiency is derived. A technique called addressable WSI is described which uses addresses to reference only good modules. By not addressing bad modules, fault-tolerance is achieved without redundancy in the conventional sense. It is argued that memory WSI avoids most of the problems of WSI construction and use.