The Digital Video Broadcasting (DVB) has proposed to introduce the Ultra-High Definition services in three phases: UHD-1 phase 1, UHD-1 phase 2 and UHD-2. The UHD-1 phase 2 specification includes several new features such as High Dynamic Range (HDR) and High Frame-Rate (HFR). It has been shown in several studies that HFR (+100 fps) enhances the perceptual quality and that this quality enhancement is contentdependent. On the other hand, HFR brings several challenges to the transmission chain including codec complexity increase and bit-rate overhead, which may delay or even prevent its deployment in the broadcast echo-system. In this paper, we propose a Variable Frame Rate (VFR) solution to determine the minimum (critical) frame-rate that preserves the perceived video quality of HFR video. The frame-rate determination is modeled as a 3-class classification problem which consists in dynamically and locally selecting one frame-rate among three: 30, 60 and 120 frames per second. Two random forests classifiers are trained with a ground truth carefully built by experts for this purpose. The subjective results conducted on ten HFR video contents, not included in the training set, clearly show the efficiency of the proposed solution enabling to locally determine the lowest possible frame-rate while preserving the quality of the HFR content. Moreover, our VFR solution enables significant bit-rate savings and complexity reductions at both encoder and decoder sides.

Scalable video coding enables to compress the video at different formats within a single layered bitstream. SHVC, the scalable extension of the High Efficiency Video Coding (HEVC) standard, enables x2 spatial scalability, among other additional features. The closed-loop architecture of the SHVC codec is based on the use of multiple instances of the HEVC codec to encode the video layers, which considerably increases the encoding complexity. With the arrival of new immersive video formats, like 4K, 8K, High Frame Rate (HFR) and 360°videos, the quantity of data to compress is exploding, making the use of high-complexity coding algorithms unsuitable. In this paper, we propose a lowcomplexity scalable coding scheme based on the use of a single HEVC codec instance and a wavelet-based decomposition as preprocessing. The pre-encoding image decomposition relies on well-known simple Discrete Wavelet Transform (DWT) kernels, such as Haar or Le Gall 5/3. Compared to SHVC, the proposed architecture achieves a similar rate distortion performance with a coding complexity reduction of 50%.

Current increasing effort in the television industry towards High Dynamic Range (HDR) imaging has raised the issue of the compression of HDR content. Offering a higher peak luminance and wider color gamut, HDR video introduces new challenges to the state-of-the-art video codecs such as High Efficiency Video Coding (HEVC) or VP9, which have been designed and optimized for the compression of Standard Dynamic Range (SDR) content. This study presents a performance comparison between HEVC and VP9 in the HDR context through both objective and subjective evaluations. The experimental objective results have shown that HEVC offers from 0.6% to 38.2% bit rate savings over VP9 depending on the objective metric which is used. The subjective study demonstrated that, on average, bit rate savings greater than 47.7% can be achieved by HEVC for the same perceived quality as VP9.

International audienceLow power design is a primary concern for modern battery-driven devices and video applications such as video decoding are often the most resource intensive applications of consumer electronics devices. Modern embedded processors are now proven to support video applications with software. They are also equipped with advanced features including Dynamic Voltage Frequency Scaling and Dynamic Power Management in order to reduce their power consumption. High Efficiency Video Coding (HEVC) is the latest MPEG video standard offering state-of-the-art compression rates and advanced parallel processing solutions. This paper presents a low power real-time software architecture for a HEVC decoder. Software decoding fosters short time-to-market as it relies on software designs for a general purpose processor. The proposed architecture exploits the characteristics of the multicore ARM big.LITTLE System-on-a-Chip to provide a low power design. Extensive power measurements as well as real-time metrics are provided to compare the proposed architecture with state-of-the-art

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