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In this paper we discuss issues arising in the design of highly pipelined VLSI circuits for high-speed signal processing applications. Problems such as clock skew, buffer design, clock distribution network, and timing simulation are addressed, and methods of alleviating them are presented. The impact of technology on the degree of pipelining is discussed. Some design examples, including an 8-bit systolic multiplier fabricated in 2.5 micron CMOS technology and tested up to 70 MHz multiplication rate, are presented. The extension of this design to a systolic multiply-add/accumulate chip and its applications are briefly discussed.

The ITU-T Recommendation G.1070 is a standardized opinion model for video telephony applications that uses video bitrate, frame rate, and packet-loss rate to measure the video quality. However, this model was original designed as an offline quality planning tool. It cannot be directly used for quality monitoring since the above three input parameters are not readily available within a network or at the decoder. And there is a great room for the performance improvement of this quality metric. In this article, we present a real-time video quality monitoring solution based on this Recommendation. We first propose a scheme to efficiently estimate the three parameters from video bitstreams, so that it can be used as a real-time video quality monitoring tool. Furthermore, an enhanced algorithm based on the G.1070 model that provides more accurate quality prediction is proposed. Finally, to use this metric in real-world applications, we present an example emerging application of real-time quality measurement to the management of transmitted videos, especially those delivered to mobile devices.