In this paper, an output capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) is implemented. To increase the current efficiency, low quiescent current less than 10 µA is used. The stability problem arising from the low bias current is overcome by applying two kinds of compensation methods. By drawing the pole-zero plot using the open-loop transfer function obtained by the small-signal modeling, the stability of the proposed LDO is guaranteed to be less than 70 mA. By using the proposed compensation methods, two zeros of the right-half plane (RHP) can be placed in the left-half plane (LHP) to prevent lagging and reduce the on-chip compensation capacitor. The current efficiency of the proposed LDO is 99.99% at the load current of 70 mA.INDEX TERMS Low-dropout regulator (LDO), current efficiency, low quiescent current, nested Miller compensation (NMC), reverse nested Miller compensation (RNMC), active feedforward compensation (AFFC).

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

In this paper, a fully-integrated dual-mode X-band radar transceiver that supports Doppler radar and frequency modulated continuous wave (FMCW) radar is proposed. To remove large off-chip DCblocking capacitors in the Doppler mode, the double-conversion technique and local oscillator (LO) chopping technique are introduced. These techniques remove the DC offset and makes the transceiver more robust to the TX to RX leakage. In addition, they also improve the noise figure (NF) by filtering out 1/f noise of the analog baseband. The FMCW radar is realized using a direct-conversion receiver and a chirp generator. The chirp generator consists of a frequency sweep generator (FSG) and a fractional-N phaselocked loop (PLL). All the analog baseband components including a programable gain amplifiers (PGA) and 1/R 4 range compensation filters are integrated on the chip as well as a bandgap and low-dropout regulators. The operating frequency is from 9.7 to 12.3 GHz, which consumes 216 mW in Doppler mode and 201.6 mW in FMCW mode from a 1.2-V supply voltage. The maximum chirp bandwidth is 750 MHz and the maximum receiver gain is 76 dB with 6-dB gain step. The chip size of the transceiver is 7.68 mm 2 including all the pads.

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