The impact of microsecond laser annealing at 1325°C on physical and electrical characteristics of HfxZr1−xO2 is compared to films annealed at 1000°C for 5s by a conventional rapid thermal process (RTP). Atomic force microscopy analysis shows that laser annealed HfxZr1−xO2 is smoother and void free, while RTP annealed HfxZr1−xO2 exhibits void formation and is rough. The x-ray diffraction analysis revealed higher degree of tetragonality on laser annealed film, particularly for Hf0.5Zr0.5O2 and ZrO2. Furthermore, laser annealed HfxZr1−xO2 devices have good electrical properties (well behaved CV, low gate leakage, and good mobility) whereas RTP annealed devices are not functional.

Integration of porous ultralow-dielectrics into advanced copper interconnect scheme has been a challenge. Among other issues, metal diffusion/drift into interconnected pores consequently leading to the degradation of dielectrics is a concern. In the present work, the electrical stability of the metal-insulator-semiconductor ͑MIS͒ capacitors with various metal electrodes on porous methyl silsesquioxane ͑MSQ͒ on thermal oxide/n-type silicon was investigated. Our results suggest that the tendency of various metal, Pt Ͻ Cu Ͻ Ru Ͻ Ta Ͻ Al, drift into porous MSQ under bias-temperature stress ͑BTS͒ corresponds to the order of metal oxidation tendency at the interface. It is noted that the metal barrier materials such as Ta and Ru perform worse than Cu itself. This behavior is similar to metal drift in organosiloxane polymer reported earlier ͓Appl. Phys. Lett., 79, 1855 ͑2001͔͒. Furthermore, as-prepared MIS capacitors with Cu electrodes show stable capacitance-voltage characteristics under a moderate BTS of 150°C and 0.5 MV/cm. Under the same BTS, a deterioration of the MIS capacitors with increasing exposure time in air is observed. The electrical stability is fully restored after being annealed at an elevated temperature of 350°C in a reducing ambient. The degradation of the MIS capacitors over time is attributed to the permeation of oxygen and moisture through interconnected pores, which consequently facilitate the formation of interfacial Cu oxide. The electrical stability of MIS capacitors with Ta electrodes however does not exhibit improvement by such annealing because of their greater heat of oxide formation. The MIS capacitors with Al electrodes on N 2 O-plasma treated porous MSQ show less metal drift than Al on porous MSQ, suggesting that the intrinsic property of metal oxide determines whether the oxygen contained in the dielectrics assists or inhibits the metal-related activities.Continuous device shrinkage beyond the 90 nm node results in interconnect delay becoming increasingly important in limiting the performance of integrated circuits ͑ICs͒. Industry has shifted to copper instead of conventionally used aluminum as the interconnect metal because copper has better conductivity and is less susceptible to electromigration. However, to significantly increase the performance of the future generation devices, copper needs to be integrated with ultralow-dielectrics ͑ Ͻ 2.5͒. 1 The shift of interlayer dielectric has been from silicon oxide ͑ = 4͒ to low-dielectrics ͑ Ͻ 3͒ and is proposed to go finally to ultralow-materials ͑ Ͻ 2.5͒. Each generation of dielectric materials has different characteristics thus creating various challenges associated with IC fabrication and device reliability. Ultralow-dielectrics are generally porous and scalable, i.e., their value can be reduced by increasing the porosity without changing the material. 2 Though, some issues can be addressed by the use of the ultralowdielectrics, these materials introduce their own set of challenges. Molecules, atoms, and ions placed anywhere within th...

The thermal stability of chemical vapor deposited ͑CVD͒ Parylene N used as a pore sealant has been evaluated. Parylene N pore sealing is shown to have a thermal stability up to 400°C in an Ar-3% H 2 forming gas ambient. A 1 nm thin film of Parylene N remains effective at blocking Co precursor penetration into porous methyl silsesquioxane ͑MSQ͒ during the CVD of Co, even after being annealed at temperatures up to 400°C. The leakage current improvement of pore sealed MSQ with an Al electrode is also maintained after a 400°C anneal. In addition, the thermal stability of thin Parylene N films themselves has been verified up to 400°C.As the semiconductor devices continuously shrink in size, the issues associated with resistance-capacitance ͑RC͒ delay, line-to-line capacitance, and power consumption become more critical to device performance. One of the most straightforward ways to improve device performance is to introduce dielectrics with lower dielectric constants ͑low-k͒ in Cu interconnect technology, and consequently reduce the RC delay. 1 For future generation logic integrated circuits ͑ICs͒, the reduction of RC delay requires the successful integration of a low-k material with a bulk dielectric constant of less than 2.0. 2 It is generally accepted that the introduction of porosity is necessary to satisfy the low-k material requirements of advanced IC devices. However, the porosity contained in low-k dielectrics leads to a number of undesirable properties such as inferior mechanical properties and susceptibility to the penetration of precursor molecules and solvents. These problems can be avoided to some extent by sealing the porous low-k material surface. A review of the currently proposed pore sealant technologies has been presented by Maex et al. 3 Jezewski et al. 4 demonstrated that chemical vapor deposited ͑CVD͒ poly ͑p-xylylene͒ ͑Parylene N, or PPX͒ thin films can act as effective pore sealants to prevent precursor penetration into porous methyl silsesquixane ͑MSQ͒ during subsequent metallorganic CVD deposition. Juneja 5 has shown that even a Parylene layer as thin as 1 nm is sufficient to seal porous MSQ based on positronium annihilation lifetime spectroscopy measurements. In addition, Juneja found that the dielectric breakdown strength of MSQ increases from 3 to 5-6 MV/cm after pore sealing. This improvement has been attributed to the difference between the original metal/porous MSQ interface and the metal/parylene sealed MSQ interface. Bae et al. 6 studied the adhesion properties of sputter deposited Ta on porous MSQ and found a substantial improvement of adhesive strength after sealing pores with Parylene N. They concluded that the polymer layer acts as a toughening media on the porous MSQ surface. Additional advantages of using Parylene N as a pore sealant include its capability for selective deposition 7 as well as the fact that Parylene N itself is a low-k material ͑k = 2.65͒ and thus the effective dielectric constant of the scheme does not appreciably change after pore sealing. 8 Among all these d...

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In this work, the adhesion of CVD dielectric caps to ULK MSQ spin-on dielectric materials with k values of 2.2 and 2.0, and a ULK CVD material with a k value of 2.7 is presented. A substantial improvement in cap adhesion to both the k2.2 ULK MSQ and the k2.7 ULK CVD material is demonstrated. The improvement is obtained using a low-k CVD glue material between the ULK dielectric and the subsequent cap material and/or by optimizing the CVD cap film deposition. Four-point bend measurement of adhesion strength is used to quantify the improvement in interface adhesion. The improvement in CVD cap adhesion is demonstrated to be strongly dependent upon both the glue layer film and the cap deposition conditions. While optimization of the CVD cap materials results in adequate adhesion for the k2.2 ULK MSQ, these improvements are demonstrated not to extend to the k2.0 ULK MSQ film.