Multi-asset barrier contracts are path-dependent exotic options consisting of two or more underlying assets. As the dimensions of an option increase, so does the mathematical complexity of a closed form solution. Monte Carlo (MC) methods offer an attractive solution under such conditions. MC methods have an O(n -1/2 ) convergence rate irrespective of the dimension of the integral. However, such methods using conventional computing with CPUs are not scalable enough to enable banks to realize the potential that these exotic options promise. This paper presents an FPGA-based accelerated system architecture to price multi-asset barrier contracts. The architecture consists of a parallel set of Monte Carlo cores, each capable of simulating multiple Monte Carlo paths. Each MC core is designed to be customizable so that the core for the model (i.e., "model" core) can be easily replaced. In our current design, a Heston core based on the full truncation Euler discretization method is used as the model core. Similarly, we can use different payoff calculator kernels to compute various payoffs such as vanilla portfolios, barriers, look-backs, etc. The design leverages an early termination condition of "out" barrier options to efficiently schedule MC paths across multiple cores in a single FPGA and across multiple FPGAs. The target platform for our design is Novo-G, a reconfigurable supercomputer housed at the NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida. Our design is validated for the singleasset configuration by comparing our output to option prices calculated analytically and achieves an average speedup of ranging from 123 to 350 on one FPGA as we vary the number of underlying assets from 32 down to 4. For a configuration with 16 underlying assets, the speedup achieved is 7134 when scaled to 48 FPGAs as compared to a single-threaded version of an SSE2-optimized C program running on a single Intel Sandy Bridge E5-2687 core at 3.1 GHz with hyper-threading turned on. Finally, the techniques described in this paper can be applied to other exotic multi-asset option classes, such as lookbacks, rainbows, and Asian-style options.

Reconfigurable Computing, Computational Finance, FPGA, PerformanceHigh-performance computing (HPC) for many computeintensive application domains, including computational finance, is at a major crossroads. Conventional computing no longer can depend upon exploiting increased clock rate and instructionlevel parallelism to sustain performance required for the emerging compute-intensive applications. Performance is now achieved through explicit parallelism using multicore and manycore CPU and GPU processors. Increasingly, conventional HPC is ill-equipped to address escalating performance demands without resorting to massively large, energy-hungry, and expensive machines, where developers simply throw thousands (and soon millions) of processor cores at each new and demanding problem. This presentation focuses upon the principal challenges and opportunities for HPC for computational finance, why and how high-performance reconfigurable computing (HPRC) is poised to make a major impact on accelerating these applications. Emerging challenges and opportunities for FinRC (Finance RC).The banking industry is one of the most constrained computing environments around. Banks operate at the speed of the market (i.e., only as slow as the fastest exchange is transferring data), with their computing costs come directly off their bottom line (so power, cooling, and space must be minimized), and they have to satisfy sometimes contradictory regulations. The most significant challenge that banks face in their computation environments is time: every computation supports a trade that must happen before a competitor's trade is executed, and there are only 12 hours in a night to do preparatory processing before the next market day opens. Furthermore, banks have a rapacious appetite for compute cycles. For example, in recent years, this need has grown as smart order routing and advanced credit risk models have been deployed. Smart order routing requires processing that can happen at line speed on network packets in flight. New credit risk models use novel mathematics that are orders of magnitude more complicated than more traditional approaches, yet still must be calculated in the same time window. Traditionally, banks have used off-the-shelf multicore servers to perform calculations. But as other parameters of the computing environment have changed, these servers cannot keep up; this opens the door to more exotic hardware solutions like manycore, GPU, and FPGA-based reconfigurable computing.Reconfigurable computing (RC) finally ready for prime time. Vendors and the research community have demonstrated small-scale but exciting successes in applying FPGA-based RC technology for accelerating scientific and other computeintensive applications. Today's (and emerging) FPGAs finally have the computational horsepower (current generation Statix V FPGA from Altera has over a million logic elements, tens of millions of memory bits, and other built-in functions) to enable high-performance computing. The opportunity is ripe for reconfigurable supercomp...