The performance of multiple-bus interconnection networks for multiprocessor systems is analyzed, taking into account conflict arising from memory and bus interference. A discrete stochastic model of bandwidth is presented for systems in which each memory is connected either to all the buses or to a subset of the available buses. The effects of the assumptions made concerning independence among requests for different memories (spatial independence) and resubmission of blocked requests (temporal independence) are investigated systematically. The basic bandwidth model is extended to account for spatial dependence, and compared to previously proposed models. Finally, the various analytic models are shown to be in close agreement with simulation results. Q 1986 Academic Press, Inc.

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In this paper we present a high performance message transport scheme that is based upon packet routing. The advantages of our scheme are derived from two observations. The first is that given sufficient support from communications hardware, decreasing the message latency time can be much more important to total program execution time than increasing the bandwidth. The second observation is that, from the standpoint of message latency, existing routing strategies tend not to make productive use of much of their available link capacity. The scheme that we propose addresses these issues and leads to substantial performance improvements across a broad range of message loads.