General rightsThis document is made available in accordance with publisher policies. Please cite only the published version using the reference above. Abstract-This paper presents a flexible 2.45-GHz wireless power harvesting wristband that generates a net dc output from a −24.3-dBm RF input. This is the lowest reported system sensitivity for systems comprising a rectenna and impedancematching power management. A complete system has been implemented comprising: a fabric antenna, a rectifier on rigid substrate, a contactless electrical connection between rigid and flexible subsystems, and power electronics impedance matching. Various fabric and flexible materials are electrically characterized at 2.45 GHz using the two-line and the T-resonator methods. Selected materials are used to design an all-textile antenna, which demonstrates a radiation efficiency above 62% on a phantom irrespective of location, and a stable radiation pattern. The rectifier, designed on a rigid substrate, shows a best-inclass efficiency of 33.6% at −20 dBm. A reliable, efficient, and wideband contactless connection between the fabric antenna and the rectifier is created using broadside-coupled microstrip lines, with an insertion loss below 1 dB from 1.8 to over 10 GHz. A self-powered boost converter with a quiescent current of 150 nA matches the rectenna output with a matching efficiency above 95%. The maximum end-to-end efficiency is 28.7% at −7 dBm. The wristband harvester demonstrates net positive energy harvesting from −24.3 dBm, a 7.3-dB improvement on the state of the art.

Cortical inhibition plays an important role in information processing in the brain. However, the mechanisms by which inhibition and excitation are coordinated to generate functions in the six layers of the cortex remain unclear. Here, we measured laminar-specific responses to stimulus orientations in primary visual cortex (V1) of awake monkeys (male, Macaca mulatta ). We distinguished inhibitory effects (suppression) from excitation, by taking advantage of the separability of excitation and inhibition in the orientation and time domains. We found two distinct types of suppression governing different layers. Fast suppression (FS) was strongest in input layers (4C and 6), and slow suppression (SS) was 3 times stronger in output layers (2/3 and 5). Interestingly, the two types of suppression were correlated with different functional properties measured with drifting gratings. FS was primarily correlated with orientation selectivity in input layers ( r = −0.65, p < 10 −9 ), whereas SS was primarily correlated with surround suppression in output layers ( r = 0.61, p < 10 −4 ). The earliest SS in layer 1 indicates the origin of cortical feedback for SS, in contrast to the feedforward/recurrent origin of FS. Our results reveal two V1 laminar subnetworks with different response suppression that may provide a general framework for laminar processing in other sensory cortices. SIGNIFICANCE STATEMENT This study sought to understand inhibitory effects (suppression) and their relationships with functional properties in the six different layers of the cortex. We found that the diversity of neural responses across layers in primary visual cortex (V1) could be fully explained by one excitatory and two suppressive components (fast and slow suppression). The distinct laminar distributions, origins, and functional roles of the two types of suppression provided a simplified representation of the differences between two V1 subnetworks (input network and output network). These results not only help to elucidate computational principles in macaque V1, but also provide a framework for general computation of cortical laminae in other sensory cortices.

A 360x360-element very high frame rate (VHFR) burst image sensor captures images at maximum frame rate up to IO6 frame/s. This is accomplished by continuously storing the last 30 image frames a t the pixel locations. The 360x360 VHFR imager having a 2x2cm2 chip is designed in the form of 4 quadrants each with 180x180 pixels. Each pixel occupies 50x50pn2 and consists of a 337pm2 photodetector with a fill factor of 13.5% and a 3-phase 30stage (5x6) series-parallel type buried-channel CCD (BCCD) register for continuously storing the Past 30 detected image frames. The chip uses 1.5pm design rules and 1.5x3pm2 minimum-size BCCD storage elements.The architecture of the VHFR imager is illustrated in Figure 1 for an array of 2x2 pixels. Each pixel consists of a photodiode with charge-collecting well under the G, gate, a blooming barrier gate G,, a drain D, and the gate G, separating the charge collecting well from the 5-stage serial ( S ) register. The drain D is used for control of blooming during the optical (frame) integration time and for dumping the excess charge signals (excess frames) from the S register. However, the drain D could also facilitate the operation with subframe optical integration time. The 5-stage serial register coupled to a 5x5-stage parallel (P) register forms a 30-frame CCD storage at each pixel location. A block diagram of the 360x360 VHFR imager is shown in Figure 2. T h i s imager is organized into 4 quadrants to reduce transfer losses and to improve processing yield of usable quadrants. Note that all 360x360 photodetectors, PDs, have the same spacing, while the shape of the CCD pixel storage is different for upper and lower quadrants.During the image acquisition cycle, the charge signal detected by the photodetector, PD, is transferred in series into the serial BCCD register of the pixel for detection of the successive frames. After the detection of 5 frames, the detected charge signals are transferred in parallel from the S register to the P register, providing a storage for the last 30 detected image frames. The continuous storage of the last 30 frames is obtained by preceding the loading of the S register from the photodetector by a parallel transfer into the S register of the charge signals from the last row of the P register of the pixel above. This last row of 5 charge signals a t each pixel location is transferred to the dumping drain D while a new row of 5 charge signals corresponding to the next 5 frames i s transferred from the photodetector into the S register. The readout of the last detected 30 frames can be initiated aRer the loading of the S register is completed. This can be at the end of any pixel row-time. At this time, all of the BCCD storage registers of each quadrant are converted (under control of the BCCD clocks) into a single large frame-transfer type CCD readout of 180x(5+1) rows and 180x6 columns. For the 3-phase BCCD design, this charge readout involves up to 180x6~3 = 3,240 transfers in vertical direction by the parallel registers and up to 180x(5+1)x3 = 3,240 tra...

Both surface luminance and edge contrast of an object are essential features for object identification. However, cortical processing of surface luminance remains unclear. In this study, we aim to understand how the primary visual cortex (V1) processes surface luminance information across its different layers. We report that edge-driven responses are stronger than surface-driven responses in V1 input layers, but luminance information is coded more accurately by surface responses. In V1 output layers, the advantage of edge over surface responses increased eight times and luminance information was coded more accurately at edges. Further analysis of neural dynamics shows that such substantial changes for neural responses and luminance coding are mainly due to non-local cortical inhibition in V1’s output layers. Our results suggest that non-local cortical inhibition modulates the responses elicited by the surfaces and edges of objects, and that switching the coding strategy in V1 promotes efficient coding for luminance.