This article reports the development of an underwater imaging system and its trial on a moored surface buoy for in situ plankton monitoring of coastal waters. The imager features shadowless white light illumination by an orthogonal lamellar lighting design, resulting in high-quality underwater darkfield color imaging of planktonic particles in the size range of ∼200 µm to 40 mm and effective reduction of zooplankton phototaxis. Through raft and buoy trials, 46 804 plankton and suspending particle images have been annotated through a human-machine mutually assisted effort into a data set with 90 categories. In the meanwhile, a deep learning model based on a triclassification VGGNet-11 and multiclassification ResNet-18 convolutional neuron networks in a two-staged hierarchy has also been trained and developed. The model has been applied with human supervision to semiautomatically analyze a total of 1 545 187 images obtained from a buoy trial for six months from late spring to early winter of 2020. The high temporal resolution results well documented the variation of the mesoplankton community structure in two time series of 38 days in summer and 54 days in autumn of the target sea region. In addition, the dominant species in the trial period and a zooplankton outbreak that had threatened the safety of the nearby nuclear power plants were quantitatively Manuscript

Abstract:A fast-locking, high-precision and low-jitter pulsewidth control loop for high-speed pipelined ADC is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A start-up circuit was adopted to enable the pulsewidth control loop (PWCL) lock rapidly. Using SMIC 0.18 µm 3.3 V CMOS Spice process model, the simulation results show that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50 ± 1% with 10%∼90% input duty cycle from 50 MHz to 250 MHz. The rms-jitter is 73 fs at 250 MHz. Keywords: pipelined ADC, PWCL, fast-locking, low-jitter Classification: Integrated circuits References

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