In this work, the effect of multiple rework cycles (up to 5x) on reliability of lead-free assemblies has been investigated. The test vehicle was designed to capture the reliability impact of rework processes on interconnects of BGA devices, the solder joints of its adjacent components and BGA devices of clamshelled devices. The effects on high aspect ratio plated through hole (PTH) vias and microvias were also considered. A variety of BGA packages, such as FCBGA, PBGA, CABGA, etc. were selected to represent different package technologies and stress levels. The effects of multiple reworks on accelerated thermal cycling (ATC) of lead-free solder joints are extensively explored in this study,The experimental and analytical findings showed that multiple reworks significantly degraded the ATC performance of the reworked assemblies by up to 50% in terms of characteristic life. It was also found that multiple reworks affect the PTH vias significantly. The combination of increased lead-free rework temperature excursions and highend PCB aspect ratios may incur higher stresses in the PTH copper barrel. Early failures were observed post multiple reworks and the subsequent ATC test due to PTH barrel cracking. However, the effects of multiple reworks are less severe for devices with microvias compared to that with PTH vias. Multiple reworks also caused severe degradation of long term performance of devices with clamshell designs. With proper control in rework process, multiple reworks have minimum effects on the adjacent BGA solder joints.In addition, failure analysis was performed in order to study the impact of multiple rework on the microstructure of SnAgCu solder joints. It was found that the IMC layer grows thicker as the number of reworks increases; however, the IMC growth rate and morphology are dependent on the surface finish of the package substrate. The failure mode and failure mechanism after ATC were also compared for different number of rework cycles. The implications of these results for the reliability of lead-free solder joints are discussed in this paper.

The termination finish of Small Output Integrated Circuit (SOIC) and Small Output Transistor (SOT) chip components were converted from Pb-free to Sn-Pb (backward conversion) and vice versa (forward conversion). The motivation for these conversions is due to a combination of factors such as the supply chain constraints on component availability, European Union’s (EU) legislation on “Restriction of Hazardous Substances” (or RoHS), and the growth of tin whiskers on matte tin finish components. The conversions were performed using a “Robotic Stripping and Solder Dipping Process”, and the mechanical reliability of the converted components was evaluated through lead pull testing. In this experiment, a 100% (all finishes are given in weight percentage unless otherwise specified) matte tin finish was first stripped and re-plated with an eutectic Sn-Pb finish. Then, components with 100% matte tin and eutectic Sn-Pb termination finish were replaced with a Pb-free Sn-3.5%Ag-0.5%Cu (SAC305) finish. Three Printed Circuit Board (PCB) surface finishes namely Immersion Silver (ImAg), Organic Solderable Preservative (OSP), and Electroless Nickel/Immersion Gold (ENIG), were evaluated with Sn-Pb and Pb-free processes. All the assembled boards were subjected to an initial analysis, which includes visual inspection with an optical microscope and X-Ray analysis. Subsequently, a time zero analysis was performed which includes cross sectioning, Scanning Electron Microscope (SEM) analysis and lead pull testing. The pull testing was performed on a Chatillon TCM 201-SS equipment. All the leads were pulled orthogonal to the surface of the PCB. After isothermal aging at 150°C for a time period of 10 days (240 hours), cross sectioning and pull testing were performed to study its effect on Intermetallic Compound (or IMC) growth and reliability.

The electronics manufacturing industry is gradually migrating towards to a lead-free environment. During this transition, there will be a period where lead-free materials will need to coexist with those containing lead on the same assembly. The use of tin-lead solder with lead-free parts and lead-free solder with components containing lead can hardly be avoided. If it can be shown that lead-free Ball Grid Arrays (BGAs) can be successfully assembled with tin-lead solder while concurrently obtaining more than adequate solder joint reliability, then the Original Equipment Manufacturers (OEMs) will accept lead-free components regardless of the attachment process or material used. Consequently, the Electronics Manufacturing Service (EMS) providers need not carry both the leaded and the unleaded version of a component. Solder voids are the holes and recesses that occur in the joints. Some say the presence of voids is expected to affect the mechanical properties of a joint and reduce strength, ductility, creep, and fatigue life. Some believe that it may slow down crack propagation by forcing a re-initiation of the crack. Consequently, it has the ability to stop a crack. The primary objective of this research effort is to develop a robust process for mixed alloy assemblies such that the occurrence of voids is minimized. Since there is no recipe currently available for mixed alloy assemblies, this research will study and 'optimize' each assembly process step. The difference between the melting points of lead-free (217°C) and tin-lead (183°C) solder alloys is the most important constraint in a mixed alloy assembly. The effect of voids on solder joint reliability in tin-lead assembly is well documented. However, its effect on lead-free and mixed alloy assemblies has not received due attention. The secondary objective of this endeavor is to determine the percentage of voids observed in mixed alloy assemblies and compare the results to both tin-lead and lead-free assemblies. The effect of surface finish, solder volume, reflow profile parameters, and component pitch on the formation of voids is studied across different assemblies. A designed experiments approach is followed to develop a robust process window for mixed alloy assemblies. Reliability studies are also conducted to understand the effect of voids on solder joint failures when subjected to accelerated testing conditions.

The transition to lead-free assembly will have a significant effect on wave soldering operations. Since the wetting ability of lead-free solder is usually less than that of tin-lead solder, it can result in unacceptable hole fills and inconsistent top side wetting - especially in the case of thick Printed Circuit Boards (PCBs). Presently, there is very little data available on lead-free wave soldering with tin-silver-copper (SnAgCu or SAC) alloy and no-clean flux chemistry. Although some researchers and consortia recommend tin-copper (SnCu) for lead-free wave soldering, demonstrating the feasibility of using the SAC alloy for wave soldering operation can aid manufacturers to use the same alloy for both reflow and wave soldering operations. In this study, SAC 305 alloy and no-clean flux were evaluated in terms of percentage of hole fill and solderability on a 93 mil thick test vehicle with Immersion Silver (ImmAg) surface finish. The evaluation was performed on a nitrogen equipped wave soldering equipment. It has 4 preheating zones (3 convection bottom heaters and 1 infrared top heater) that provides good control to develop the required preheat profile. A partial factorial experiment was conducted to study the main effects of solder pot temperature, topside preheat temperature and conveyor speed on wave soldering performance. Wave soldering was performed after two reflow cycles. A 100% visual inspection was done for all the through hole components using a 10X microscope to determine top side wetting, percentage of hole fill, bridging, flux residue and solder balling. Thickness of the hole fill was also measured using digital X-Ray equipment. The data generated from this experiment was used to determine the 'optimum' lead-free process parameters for wave soldering using a SAC 305 alloy with a no-clean flux chemistry. The 'optimized' process parameters were then used to evaluate boards with Organic Solderability Protective (OSP) and Electroless Nickel Immersion Gold (ENIG) surface finishes. The designed experiments approach adopted to determine the optimum process settings and the research findings are explained in detail.