The impact of the stray inductances originated from interconnects in power electronics becomes crucial with the next generation of SiC devices. This paper shows that the existing layout of a railway inverter, operating with Si IGBTs already exhibits a dynamic current imbalance between paralleled modules. This will not allow using this geometry with SiC MOSFETs. A complete investigation of the electromagnetic origin of this issue has been performed. A generic circuit model has been proposed to establish a cabling rule to design a Gate Distribution Printed Circuit Board (PCB) in such a way that it compensates the power dissymmetry. An optimization strategy has been used to obtain a new geometry of this PCB, which has been validated with a time domain simulation.

No abstract

This paper aims determining the minimum decoupling capacitor Cdec for a railway traction inverter. It is defined when any increase of its value does not decrease the overvoltage at turn off anymore. A simple generic model is deduced from a full understanding of the switching cell behavior, including the effect of all stray inductances and all interactions within the switching cell. This model is used in an optimization process in order to obtain directly the minimal value of Cdec. The methodology is validated in comparison with time simulation, as well as using experimental results. It has been used to analyze the impact of the switching cell parameters on the minimum value of Cdec: switching speed, stray inductances and additional resistance have been considered.

No abstract