Motivated by the importance of the clock synchronization in wireless sensor networks (WSNs), this paper proposes a new research approach and model approach, which quantitatively analyzes clock synchronization from the perspective of modern control theory. Two kinds of control strategies are used as examples to analyze the effect of the control strategy on clock synchronization from different perspectives, namely, the single-step optimal control and the LQG global optimal control. The proposed method establishes a state space model for clock relationship, thus making dimension extension and parameter identification easier, and is robust to changes under the condition of node failures and new nodes. And through the design of different control strategies and performance index functions, the method can satisfy various requirements of the synchronization precision, convergence speed, energy consumption and the computational complexity, and so on. Finally, the simulations show that the synchronization accuracy of the proposed method is higher than that of the existing protocol, and the former convergence speed of the synchronization error is faster.

Motivated by the importance of the clock synchronization in wireless sensor networks (WSNs), due to the packet loss, the synchronization error variance is a random variable and may exceed the designed boundary of the synchronization variance. Based on the clock synchronization state space model, this paper establishes the model of synchronization error variance analysis and design issues. In the analysis issue, assuming sensor nodes exchange clock information in the network with packet loss, we find a minimum clock information packet arrival rate in order to guarantee the synchronization precision at synchronization node. In the design issue, assuming sensor node freely schedules whether to send the clock information, we look for an optimal clock information exchange rate between synchronization node and reference node which offers the optimal tradeoff between energy consumption and synchronization precision at synchronization node. Finally, simulations further verify the validity of clock synchronization analysis and design from the perspective of synchronization error variance.