Sample-time errors can greatly degrade the dynamic range of a time-interleaved sampling system. In this paper, a novel correction technique employing a cubic spline interpolation is proposed for inter-channel sample-time error compensation. The cubic spline interpolation compensation filter is developed in the form of a finiteimpulse response (FIR) filter structure. The correction method of the interpolation compensation filter coefficients is deduced. A 4GS/s two-channel, time-interleaved ADC prototype system has been implemented to evaluate the performance of the technique. The experimental results showed that the correction technique is effective to attenuate the spurious spurs and improve the dynamic performance of the system.

Flight data recorder (FDR) is key equipment for aircraft testing system. In this paper, a solid-state FDR using multichannel technique is presented. Aims at satisfying the system requirement of high recording speed and large capacity, the proposed FDR employs a multi-level parallel access structure to achieve a high recording speed system based on NAND flash. Performance evaluation based on the hardware platform is carried out. Conclusion based on the experimental results indicates that the proposed FDR offers reliable performance for recording the information during the flight in real time.

Because of its lightweight, high density, and energyefficient characteristics, NAND flash memory has been widely used as a storage medium for electronic devices in multiple areas, such as industrial electronics, biomedical image recorder and computers. However, due to its low IO performance and long operation latency, multiple techniques are applied to the NAND storage systems to overcome these drawbacks. In this paper, we present a tri-level parallel architecture to improve the bandwidth of the storage system by hiding the operation latency through controller level, chip level and die level interleaving. The evaluation results implemented on a prototype board show that the read and write throughput of the system based on the proposed architecture could be improved enormously by utilizing multiple level interleaving techniques, and the redundancy of the flash bus could be eliminated maximally. Keywords-tri-level parallel architecture; NAND flash memory; cluster-mapping scheme; biomedical image recorderI.

SAR raw data recording and playback system produces enormous influence on the SAR imaging processing. After consideration of compared with traditional magnetic disk arrays, we present an ultra-high speed recording and playback system based on NAND flash memories. Based on the hardware system, we dwell on the software mechanism of the system, which mainly focused on the packet scheduling approaches. An improved round robin packet scheduling approach and a packet prefetch approach is presented. Finally, a performance evaluation based on the hardware platform is carried out, which indicated that the proposed approaches are efficient to enhance the performance of the system.

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