In this work, the performance of copper (Cu), dielectric inserted horizontal graphene nanoribbon (Di-HGNR) interconnect, and dielectric inserted vertical graphene nanoribbon (DiVGNR) interconnects is investigated using active shielding and passive shielding techniques. However, the analysis is carried out by adapting driver-interconnect-load system. This analysis considers the interconnect length from 500 to 2000 µm for 10 nm technology node. Further, the crosstalk induced effects on various interconnect structures are examined. It is envisioned that Di-VGNR exhibits lowest propagation delay compared to Cu and Di-HGNR. Further, the in-phase and out-phase crosstalk delay among the coupled interconnect lines is determined. It is investigated that active shielded Di-VGNR has least crosstalk induced delay compared to other interconnect structures considered in this study. Therefore, Di-VGNR interconnects outperforms Cu and Di-HGNR and are best suited for future VLSI interconnects.

Booming VLSI technology has graciously facilitated down-scaling dimensions of on-chip devices and interconnects in integrated circuits (ICs) to nano-miniaturized scale. However, at nano-dimensions where added benefits of scaling are constrained by associated highly-dense on-chip nano-interconnect structures, their electro-migration effects and several limiting signal-integrity issues. These cumulatively affect the quality of signal (QoS) at output. Improving output QoS is essential for attaining faithful system performance. First, different structures and their performance of futuristic graphene based multi-layer graphene nano ribbon (MLGNR) interconnect is investigated. Then, to improve data rates and performance, efficient and novel carbon nanotube field effect transistors (CNTFETs) based ternary logic system is incorporated for the prominent nano-MLGNR interconnects. Then, QoS enhancement of highly potential DS-MLGNR interconnect is proposed using active shielding technique. Finally, is chase to further enrich QoS, adaptive least mean square (LMS) equalization technique is used at the receiver. The proposed work comprising of futuristic novel graphene interconnects with efficient ternary logic system together with adaption of several QoS improvement techniques are magnificent and panacea solution to limiting nano-interconnects in advanced ICs. Several interesting and seminal analyses such as delay, power, power-delay product, crosstalk, eye-diagram are performed that supports the novelty and effectiveness of the proposed work.

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The approach of monolithic 3D IC (M3D) integration using monolithic inter-tier-vias (MIVs) as interconnect structures is considered. Although, M3D ICs show many benefits of heterogeneous integration without significant area overhead compared to 3D ICs, reliability and thermal issues become daunting challenges to be addressed. Hence, this study focuses on electromigration issues of current density, thermal stress, and structure deformation due to temperature loading. For the analysis Cu and carbon nanotube (CNT) filler materials were chosen in MIV structure. Our analysis reveals that CNT based MIV offers two-fold higher current density and 91% lesser thermal stress compared to Cu based MIVs. Furthermore, at different voltage values, the current density profiles are examined. For the comprehensive investigations of structure deformations, temperature gradient was allowed at the ends of the MIV structure. The results show less deformations in CNT compared to Cu, based on the stress induced among them. The failure time prediction shows higher mean time to failure value of CNT based MIV than Cu based MIV.