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Inverter is truly the nucleus of electronics industry. It is the main building block of everyday appliances i.e. microwaves, power tools, battery chargers, air conditioners and computers etc. In this paper, CMOS technology has been chosen to study the transient and dc characteristics of an inverter. Feature size is the main parameter to study the voltage transfer characteristics of inverter, for which length and width of transistors is varied. Further, CMOS inverters can be paralleled for increased power to drive higher current loads. Simulations are run on cadence design tool and the schematic diagrams are drawn in virtuoso schematic editor using 180nm technology file.

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Today, Fin shaped Field Effect Transistors (FinFETs) are the foundation of the sub-nanometer technology node. The semiconductor industry endorses it in low-power (LP) and high-performance (HP) applications due to its better electrostatic control and exceptional scalability. In this paper, the structure of an inverted funnel-shaped FinFET device with a high-k stacked gate has been optimized using integrated Artificial Neural Network (ANN) and genetic algorithm (GA) approach. The comparative analysis of rectangular FinFET, trapezoidal FinFET and proposed novel shaped FinFET has also been explored. The electrical and analog performance parameters of the novel device present better performance results with respect to the other two transistors. In ANN training, the three datasets have been created by varying the metrics such as equivalent oxide thickness (EOT) and dielectric constant (k) of novel shaped FinFET device in Technology computeraided design simulator (TCAD). The amalgamation technique of ANN and GA optimization provides diminished Subthreshold Swing (SS), reduced off-current (IOFF), enhanced on-current (ION) and improved current ratio (ION/IOFF) corresponding to the optimal value of EOT and k. The new structure designed and simulated with the optimal amount of EOT and k results in outstanding performance parameters. The device metrics values, SS of 62.1 mV/dec, IOFF of 6.56×10-11, ION of 3.938×10-5 and ION/IOFF of 5.95×105 indicate that optimized device has suppressed Short Channel Effects (SCEs). The average deviatION of 3.48% between the value of ANN-GA optimized results obtained through MATLAB and TCAD simulated performance parameters justify the effectiveness of proposed FinFET.

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