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The specification of digital logic in SOL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic.

Abstract. This paper deals with a study and a mathematical model of concurrent Points of Control and Observation (PCOs) realized in Testing and Test Control Notation version 3 (TTCN-3). We study test scenarios that are gaining importance as TTCN-3 is emerging as a notation suitable for conducting load tests too. We investigate communication between parallel test components (PTCs) and analyze race conditions between the queues underlying the implemented PCOs. This way, we build an analytic model to investigate behavior of PCOs under stress conditions and to assess possible latencies messages in a TTCN-3 based load test system might suffer. We present a discrete-time Quasi Birth-Death process to predict performance indices of test components and we propose to use the results to avoid indefinite postponement in the communication of PTCs. Also, we aim to use the model for calculating traffic intensity limits under which it is feasible to use TTCN-3 for load testing. Furthermore, we present the output of the model together with an example load test scenario that is vulnerable to that types of latencies.

We study the problem of patching, i.e., modifying the behavior of an existing system. We consider systems modelled as finite state machines (FSMs), and define edit operators for them based on a traditional fault model. We argue that sequences of edit operations can be considered as models of patches defining modifications to an FSM system. We utilize recent results in graph matching theory as mathematical foundations. We introduce a new type of problem which we call the optimal patch or optimal update problem: Given an FSM M modeling the behavior of an existing system and an other machine M modeling a new design, find an optimal patch, i.e., the edit operations changing M to M that are minimal according to a given cost function associated with the edit operations. We analyze the complexity of the problem, and conclude that it is unlikely to have a polynomial time solution for it. We also show that the problem can be easily transformed to a state-space search problem, for which many heuristic approximation algorithms have been developed.

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