A new method for reducing output noises in the R-2R resistor ladder digital-analog converter (DAC) is presented. The main reason for the output noises in R-2R resistor ladder DAC is the disadvantages and non-ideal features of the operational amplifier (Op-Amp). In case of the low numbers of the input combination there can be an output voltage without noises, because the voltage-error for the OpAmp in case of low output voltage is very small. But the low output voltage can be not the exact voltage because many times the 0 voltage on the negative input of the OpAmp forms is not clear. The high output voltage of the OpAmp can be more exact, but it will have noises because of the conflict between the voltage corresponding to the difference of the input voltages and the voltage corresponding to the current coming from the R-2R ladder. Using the new method, the output voltage of the R-2R resistor ladder DAC will be exactly in the full input combination range, and it will have almost no noise. In the primary 4-bit R-2R DAC designed in the 32 nm technology the INL (integral nonlinearity error) in case of 0000 input combination is 0.2 V, and the noise-error in case of 0101 input combination is 0.065 V. In the optimized R-2R DAC, the maximum INL error is 0.02 V at 0010 input combination and the maximum noise-error is 0.005 V at 0001 input combination. Using the method, the area of the circuit increases by 7%. As this disadvantage is very small the new approach is very preferable to use for accurate output signal in the R-2R resistor ladder DAC.
A new approach for reducing output noises in the level-shifter is presented. The level-shifters which are intended for making the high-voltage amplitude signal from lowvoltage amplitude signal, has a big issue related to the output noises. The noises that come from parasitic capacitances and other sources become much higher in the output as the circuit increases the amplitude of the input signal in the output, so it also increases the noises. These level-shifters also have the delay time issue. The delay time range between the input signal and output signal is not so low. Using the capacitances in the output for reducing the noises can increase the delay time range, which is not a good feature for the circuit. The new method reduces the output noises without increasing the delay time range, also it increases the area of the circuit with a little percent. By using this method in 32nm technology, the area of the circuit increases by 14% and the noise error decreases by 68%
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