This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty.

One of Sandia's research efforts is to reduce the end-to-end communication delay in a paralleldistributed computing environment. GIGAswitch is DEC's implementation of a gigabit local area. network based on switched FDDI technology. Using the GIGAswitch, we intend to minimize the medium access latency suffered by shared-medium FDDI technology. Experimental results show that the GIGAswitch adds 16.5 microseconds of switching and bridging delay to an end-to-end communication. Although the added latency causes a 1.8% throughput degradation and a 5% line efficiency degradation, the availability of dedicated bandwidth is much m,)re than what is available to a workstation on a shared medium. For example, ten dil"ectly connected workstations each would have a dedicated bandwidth of 95 Mbps, but if they were sharing the FDDI bandwidth, each would have 10% of the total bandwidth, i.e., less than 10 Mbps. In addition, we have found that when there is no output port contention, the switch's aggregate bandwidth will scale up to multiples of its port bandwidth. However, with output port contention, the throughput and latency performance suffered significantly. Our mathematical and simulation models indicate that the GIGAswitch line efficiency could be as low as 63% when there are nine input ports contending l:_r the same output port. In a distributed parallel computing environment, output contention often involves the contention for a server's resources. Our data indicate that the delay introduced by contention at the server workstation is 50 times that introduced by the GIGAswitch. We conclude that the GIGAswitch meets the performance requirements of today's high-end workstations and that the switched FDDI technology provides an alternative that utilizes existing workstation interfaces while increasing the aggregate bandwidth. However, because the FDDI standard limits. the available bandwidth to 100 Mbps and the speed of workstations is increasing by a factor of 2 every 1.5 years, the switched FDDI technology is only good as an interim solution.