During the past few years, different techniques for development of frequency-selective filters have been developed. Each of these variations has its own merits and disadvantages. However, there is a need to propose a well-organized procedure for design of a digital filter and comparing all implementation methods together and providing the designers with quantitative measures on usability, area, and speed of each method. In this paper, we first go through the digitization procedure of a general digital filter and its optimization using simulated annealing (SA). Also, we introduce different (serial, parallel, bit-level and word-level) implementation-techniques and give a comparative view of the scene. In order to gain a better performance, power and area characteristics, a synthesis technique which simultaneously performs scheduling, binding and module selection is presented, using genetic algorithm (GA). The detailed implementation of these alternatives is compared in terms of delay and area when implemented in a Xilinx Virtex-II FPGA.