The design reuse methodology, which has been developed at the VCDS Project, is a SoC design methodology to reduce the SoC design time using high level design intellectual properties named as Virtual Cores (VCores). In this paper, we propose the VCore based design methodology to synthesize the SoC architecture from the system level specification. This synthesis methodology generates an initial architecture that consists of a CPU, buses, I/Os peripherals, and RTOS (Real Time Operating System), and makes tradeoffs between hardware and software on assigned software VCores and hardware VCores models to the architecture. The results of an architecture level design experiment using the proposed methodology shows that the partial automation of the communication refinement process, allied with design reuse, accelerates the architecture synthesis, thus reducing the design time required to design an architecture.