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A CMOS SOG(Sea-Of-Gates) that contains 177K raw gates corresponding to 1 . 4 M transistors and with a delay time of as fast as 150ps, has been developed by applying a 0.8um CMOS technology. The SOG can accommodate RAY of either a high density type of 64K bits maximum or a high speed type with 6ns access time, or mixing of the both. The SOG contains 1856 1/0 buffers in the peripheral area of the die, providing high flexibility for interfacing the circuits to be connected to the SOG.

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 pm, has been developed.The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to h'gh reliability of 5 V operation. BCD' structure is employed for 1.0 pm N-channel MOS transistor, which realizes both high current gain and very high reliability for hotelectron degradation. Al/MoSix/Ti contact system and. interlevel dielectric planarization process have been newly developed for high performance interconnections.To experimentally verify the effectiveness of the technology with 1.0 pm design rule, a 7K gate-array has been fabricated and its electrical characteristics has been examined.

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