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Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.

In the featuring VLSI era, compact

Abstract. Power efficient SRAM cell with temperature invariant data retention is very vital component in the design of deep-submicron Static memories. A novel ultra low power stable 8T-SRAM cell for 50 nm CMOS technology is analyzed for data retention property in this paper. It exhibits power reduction both in active mode and standby modes of operation and ideal data retention at operating temperature range of -50 0 C to 150 0 C. Two additional NMOS transistors, one each in the pull down path the two inverters of standard 6-T SRAM cell utilize self correcting feedback to provide this performance. During the active mode one of the inverters (OFF) utilizes stack effect and the other inverter (ON) uses cascode amplification property to reduce power dissipation. Sub threshold leakage power is reduced by utilizing stack effect in the idle mode. Simulations using BSIM 4 models for 50nm technology and supply voltage value of 0.5V, indicate about 23X power savings in active mode and 28 X times in stand-by(data-retention) mode at 50 0 C. The logic 1 data of the SRAM cell is retained at 499.74 mV for V DD of 500mV during standby (data retention) mode.