Experiments and modelling of new three-terminal heterojunction phototransistors with double emitters (DE-HPTs) but no base contact are reported for comparison with single-emitter HPTs (SE-HPT) without base electrode and conventional HPTs with a base electrode using the same epi-layers. Double emitters having a different area ratio (A 1 : A 2 ) but a fixed total area together with a collector form a three-terminal device. As a voltage-bias emitter instead of a current-bias base is used, a DE-HPT exhibits an enhanced collector photocurrent in comparison with a SE-HPT with the same total emitter area. Experimental results reveal that 2 : 1 and 1 : 1 DE-HPTs exhibit a 1.85-and 1.5-fold optical gain, respectively, over that from a SE-HPT. Other key features of a DE-HPT include the following:(1) the differential emitter voltage used is as small as several hundred millivolts, (2) not only a positive but also a negative voltage can be used to enhance the final collector photocurrent and (3) polarity-dependent characteristics are obtainable for an A 1 : A 2 DE-HPT. Moreover, a new circuit model with three sets of parallel diodes is proposed to explain the performance enhancement and polarity-dependent behaviours. Theoretical results are in very good agreement with experimental ones and indicate that more than three-fold enhancement is expected.

Heterojunction doped-channel field-effect transistors (HDCFETs) with a self-built field-plate gate formation were fabricated and proposed in this work. Arrangement of Schottky metal across a step undercut between the Schottky barrier and the insulator-like layer is the key process to produce a self-built field-plate gate. A controllably reduced gate length and a self-built field plate were simultaneously formed. Effects of gate-metal length, field-plate length and insulator thickness on HDCFET performance were also investigated. Simulated results reveal that higher currents, lower electric fields, better device linearity and larger output power are expected by offsetting the Schottky metal towards the drain side. A HDCFET with gate-metal length of 0.4 µm, field-plate length of 0.6 µm and insulator thickness of 120 nm was successfully fabricated for comparison to that with a 1 µm traditional planar gate. Current density (451 mA mm −1 ), transconductance (225 mS mm −1 ), breakdown voltages (V BD(DS) /V BD(GD) = 22/−25.5 V), gate-voltage swing (2.24 V), unity current-gain and powergain frequencies ( f t /f max = 17.2/32 GHz) are improved as compared to those of a 1 µm gate device without field plates. At 1.8 GHz and V DS of 4.0 V, maximum power-added efficiency of 36% with output power of 13.9 dBm and power gain of 8.7 dB was obtained. Saturated output power and linear power gain are 316 mW mm −1 and 13 dB, respectively.

Depletion-mode Al 0.24 Ga 0.76 As/In 0.22 Ga 0.78 As double-heterojunction high electron mobility transistors (DH-HEMTs) were fabricated with an as deposited gate to compare with those with a buried gate by annealing. Instead of a recessed gate, a buried gate used to control the distance between the gate and channel (and hence the aspect ratio) improves the series resistance. Measured transconductance of 150 mS mm −1 and an open-drain voltage gain of 136 for the DH-HEMT with an as deposited gate are enhanced to 175 mS mm −1 and 160 for the DH-HEMT with a 330 • C annealed gate. Good device linearity is also obtained with a low second harmonic to fundamental ratio of 3.55%. The measured maximums f t s ( f max s) are 13.5, 13.5 and 14.5 (35, 37, and 37.5) GHz for DH-HEMTs with an as deposited gate, and with 280 • C and 330 • C annealed gates, respectively. At a measured frequency of 2.4 GHz, the DH-HEMT with a 330 • C annealed gate exhibits the highest PAE = 44.8% at V DS = 3 V and V GS = −1.0 V and the lowest F min = 1.89 dB at V DS = 3 V and I D = 200 mA mm −1 .

V-gate heterojunction doped-channel field-effect transistors (HDCFETs) with a 0.12 µm gate-metal footprint were fabricated through a 1 µm patterned photoresist using conventional optical lithography. The measured transconductance and output conductance are 200 and 3.5 mS mm −1 , respectively, resulting in a high open-drain voltage gain of 57. In spite of higher unity-current gain and unity-power gain frequencies (21 and 32 GHz) as compared with those (9.5 and 17 GHz) of a 1 µm planar-gate HDCFET, the frequency enhancement for a V-gate HDCFET with such a short 0.12 µm gate-metal footprint is not very significant. Simulated results reveal that both the triangular-metal fringe and sacrificial layer play an important role in HDCFET dc and ac performances. Experimental and simulated results reveal that (1) the triangular-metal fringe is advantageous to improve short-channel effects and to enhance the dc performance, (2) the gate fringing capacitance due to the triangular-metal fringe and the 0.455 µm sacrificial layer contributes 60% of capacitance to the total gate-to-source capacitance, and (3) even if there is no sacrificial layer upon the Schottky layer, the triangular-metal fringe still contributes 15% of capacitance to the total gate-to-source capacitance.