Abstract-This paper describes a 10-b 20-Msample/s analogto-digital converter fabricated in a 0.9-pm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-anddistortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mmz and dissipates 240 mW.

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An efficient architecture for a pipelined AID converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a sampling rate of over 50 Msamplesh has been achieved in a 0.9-pm CMOS technology.