No abstract

This paper describes the design of a transmit PLL circuit at 24GHz in a 0.13µm CMOS technology. This transmit PLL is made with fully differential circuits to reject common mode noise. The VCO output frequency is 24GHz and the IF frequency is 400 MHz. In order to take advantage of the fully differential VCO, a differential charge pump and loop filter are developed. This differential charge pump draws no DC current when PLL is in lock. The supply voltage for this PLL is 1.5V. The loop bandwidth is 500 KHz and the in band phase noise at 100 KHz offset is -112dBc. The settling time is 220 ns.

We report a compact 802.11b/g/n MIMO SoC with fully integrated transceiver, on-chip PMU including dcdc converters, PHY, MAC, PCIe and a non-volatile memory. The transceiver includes on-chip PA, LNA and T/R switch. Fabricated in 90nm standard digital CMOS technology, this IC consumes 663/878mW (Rx/Tx 54Mbps) with an area of approx 33mm2. A peak saturated power of 24dBm is achieved at antenna.