In this work, we report a mapping of charge transport in silicon nanocrystals (nc-Si) embedded in SiO2 dielectric films with electrostatic force microscopy. The charge diffusion from chargednc-Si to neighboring uncharged nc-Si in the SiO2 matrix is found to be the dominant mechanism for the decay of the trapped charge in the nc-Si. The trapped charge and the charge decay have been determined quantitatively from the electrical force measurement. An increase in the area of the charge cloud due to the charge diffusion has been observed clearly. In addition, the blockage and acceleration of charge diffusion by the neighboring charges with the same and opposite charge signs (i.e., positive or negative), respectively, have been observed.

The presence of Al nanocrystals ͑nc-Al͒ in AlN thin films is found to enhance the current conduction of the thin film system greatly due to the formation of tunneling paths of nc-Al arrays, and the nc-Al/ AlN system shows a quasi-two-dimensional transport following a power law. However, charge trapping in nc-Al reduces the current conduction because of the increase in the tunneling resistance and/or the breaking of some tunneling paths due to Coulomb blockade effect. The current conduction also evolves with a trend towards one-dimensional transport due to the breaking of some transverse tunneling paths as a result of the charge trapping.

In this work, the unique synthesis of mechanically milled silicon nanocrystals (Si nc) embedded in tetraethylorthosilicate (TEOS) thin films is reported. A series of Si nc, with sizes ranging from 10to25nm, have been synthesized using mechanical milling. For both the milled Si nc and milled Si nc embedded in TEOS thin film, infrared absorption and photoluminescence results show that the photoluminescence (PL) is not a consequence of quantum confinement, amorphous Si component, or Si–OH or Si–H bonds. The defects, such as nonbridging oxide hole centers (NBOHCs), in amorphous SiO2 are probably the dominant mechanism for the PL of milled Si nc embedded in TEOS thin films. In addition, PL excitation results reveal oxidation-induced strain between the interfaces of milled Si nc∕SiO2 has also generated a new luminescence center. This luminescence center is similar to the NBOHCs attributed to interfacial strain.

A technique for fabricating submicron free-standing silicon pillars has been developed. The silicon pillars have a high packing density, and aspect ratios over 50:1 can easily be achieved. Photoassisted electrochemical etching in hydrofluoric acid is used to etch deep macropores in n-type silicon wafers which have been patterned by standard photolithography. The regular macropores can be used for fabricating photonic band-gap structures. The bulk silicon remaining between the close-packed macropores is oxidized. Free-standing pillars are then formed by subsequently wet etching the silicon dioxide. The pillars are the initial structures for forming quantum wires using further oxidation and etch steps.

This paper reviews the current status of the growth of fully doped HgCdTe (MCT) devices by metalorganic vapor phase epitaxy (MOVPE). The current reactor system has been developed to produce 3-inch diameter epitaxial layers compatible with slice-scale processing. The new reactor system has achieved routine epitaxial growth of MCT with good morphology onto both gallium arsenide (GaAs) and GaAs on silicon (Si) wafers that were oriented (2-8°) off (100) orientation. The density of surface defects (so-called ''hillocks''), typical of MOVPE growth on such orientation substrates, has been reduced to ,5 cm ÿ 2 at a sufficient yield to make the production of low cluster defect 2D arrays possible. Alternative growth experiments onto cadmium telluride (CdTe) on Si substrates with (211)B orientation have also been performed to investigate their usefulness for infrared focal plane array (IRFPA) applications. Si substrates give better thermal expansion match to the read out Si circuits (ROIC). The horizontal reactor cell design has a graphite susceptor with a rotating platen capable of using substrates up to 4-inch diameter. Work, however, has concentrated on 3-inch diameter GaAs and GaAs on Si wafers substrates in the reactor, and these reproducibly demonstrated good compositional and thickness uniformity. Cut-off wavelength and thickness uniformity maps showed that there was sufficient uniformity to produce twelve sites of large format 2D arrays (640 3 512 diodes on 24-mm pitch) per slice. Minority carrier lifetimes in heterostructures is an important parameter and some factors affecting this are discussed, with special emphasis on As-doped material grown under various growth conditions in an attempt to reduce Shockley-Read (S-R) trap densities. New data are presented on trap densities and theoretical fitting of lifetimes in MOVPE material. Fully doped heterostructures have been grown to investigate the device performance in the 3-5 mm medium-wave IR (MWIR) band and 8-12 mm long-wave IR (LWIR). These layers have been fabricated into mesa arrays and then indium-bumped onto Si multiplexers. A summary of the 80-K device results shows that stateof-the-art device performance has been demonstrated in MOVPE-grown device structures.