ISBN: 978-1-4244-3933-1International audienceIn this paper a Programmable/Stoppable oscillator is designed based on a Self-Timed Ring. A new model is proposed to calculate the oscillation frequency of the ring. Different solutions for introducing programmability to self timed rings are designed and implemented. Using different techniques, the implemented oscillator achieves a frequency range of 3GHz down to 400MHz with a smallest step of 100MHz

International audienceThe design of complex systems-on-chip (SoCs) in the upcoming complementary metal-oxide-semiconductor (CMOS) technologies has become increasingly challenging due to the high levels of integration, the excessive energy consumption, the clock distribution problems and the increased process variability impact. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency domains and propose an efficient control algorithm for on-the-fly workload monitoring and management. This algorithm is able to cope with the technology-related variability and with the variable workload of the system. It dynamically controls the speed of the different voltage-frequency islands with respect to the process variability impact on each island. Within this work, a new clock synchronization scheme is also presented. Simulation results demonstrate the effectiveness of our approach in guarantying the average speed performance of the system under different cases of the process variability effect while keeping reduced the overall system energy consumption. Moreover, this is achieved with a small area overhead. The results are validated on a MIPS R2000 processor node using the 45 nm CMOS technology from STMicroelectronics

Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bits which leads to reduce the consumed bandwidth. The MATLAB simulation and the field programmable gate array (FPGA) implementation will be provided in this paper to validate the proposed concept.

The design of integrated circuits, especially System-on-Chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs -which adopt the Globally Asynchronous Locally Synchronous (GALS) paradigm -require specific power supplies and clock generators as actuators and dedicated sensors. The problem faced by the designers is the non-uniform and non-predictable behaviour of such systems which embed several microprocessors and complex Network-on-Chips (NoC). In these conditions, the control laws are difficult to establish. Moreover, with the technology shrink, the control needs are increased. In order to reach an acceptable fabrication yield, the clock synchronisation -based on the assumption that the critical path is shorter than the clock period -is impracticable with large SoCs which are divided in multiple clock domains. This is why specific sensors are used to evaluate the fabrication process quality and the local environmental parameters (voltage, temperature) in each clock region in order to determine the appropriate clock frequency which does not violate the local timing constraint. All these systems are fed back and required well-suited control techniques able to manage process variability as well as energy or speed.978-1-4244-4602-5/09/$25.00 ©2009 IEEE

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