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Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels which efficiently route transactions between SW and HW entities through the on-chip communication network with respect to quality-of-service and realtime requirements. The goal is to methodically simplify MPSoC design by systematic HW/SW interface abstraction, thus enabling early SW verification, rapid prototyping and fast exploration of critical design issues. With TRAIN, we present our implementation of such a VTL architecture for Virtex-II Pro and PowerPC and illustrate its efficiency by experimentation. end, a flexible and scalable HW/SW communication architecture is required which from the programmer's point of view fully retains all TLM channels as virtual channels in the final system implementation. The key features that such an architecture should provide are:Flexibility: The hardware part of the architecture should be highly flexible and scalable, enabling each processor core to be connected to an arbitrary number of on-chip communication networks. Performance:The HW/SW interface should deliver highest possible data transfer rates according to the underlying communication subsystems. Adaptability:The VTL should be highly retargetable, rendering any re-engineering of MPSoC components unnecessary. For software components, TLM channel interface method calls such as put and get should be transparently mapped to the HW/SW interface. Hardware components should be accessible independently from their communication protocol.Configurability: Each TLM channel of the high-level system model should be represented by a virtual communication channel in the implementation model. Virtual

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